IPC/Capabilities Overview

[M. Edward Borasky]

> -----Original Message-----
> From: l4-hackers-bounces at os.inf.tu-dresden.de 
> [mailto:l4-hackers-bounces at os.inf.tu-dresden.de] On Behalf Of 
> Jonathan S. Shapiro
> Sent: Wednesday, December 31, 2003 4:37 PM
> To: rudykoot at mithrill.org
> Cc: L4 Hackers List
> Subject: Re: IPC/Capabilities Overview
> 
> 
> I have already responded to the substance of Rudy's note, so 
> just a few brief points here.
> 
> On Wed, 2003-12-31 at 11:39, Rudy Koot wrote:
> > This goes in against their believe that "A computers get 
> faster memory 
> > acess
> > get relativly slower, therefore memory access should be 
> avoided during IPC". 
> 
> Based on history of processor architecture over the last 30 
> years, this belief is very well motivated. The problem is 
> likely to get worse, not better.

Yes, memories get *bigger* but not faster. So memory hierarchies get deeper.
I wonder if operating systems shouldn't have a "deeper hierarchy" as well
... A "nanokernel" that lives in the processor and its registers, a
"microkernel" that lives in the level 1 cache, etc. 

-- 
M. Edward (Ed) Borasky
mailto:znmeb at borasky-research.net
http://www.borasky-research.net
 
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