Fiasco.OC with ARM TrustZone

[Adam Lackorzynski]

On Thu Jun 06, 2013 at 18:58:42 +0800, Chao-Jui Chang wrote:
> The boot message is the same for both "Standard mode" and " TrustZone
> normal size"
> 
> ### Cut start ###
> Hello from Startup::stage2
> Number of IRQs available at this GIC: 160
> FPU0: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard, p:
> dbl/sngl
> Watchdog initialized
> SERIAL ESC: allocated IRQ 85 for serial uart
> Not using serial hack in slow timer handler.
> Welcome to Fiasco.OC (arm)!
> L4/Fiasco.OC arm microkernel (C) 1998-2013 TU Dresden
> Rev: r54 compiled with gcc 4.5.2 for Samsung Exynos    []
> Build: #60 18:37:23 CST 2013
> 
> Timer for CPU0 is at IRQ 28
> Calibrating timer loop...

So timer not working or something with interrupts not working.
Could you check whether the mct is working ok, e.g. by adding a few
relevant printfs?

> Here is "TrustZone secure side"
> ### Cut start ###
> Hello from Startup::stage2
> 
> Number of IRQs available at this GIC: 160
> GIC: Switching IRQ 32 to secure
> GIC: Switching IRQ 33 to secure
...
> ### End ###
> It stop here.
> 
> Any idea?

I'm wondering why so many IRQs are allocated so early in boot-up?



Adam
-- 
Adam                 adam at os.inf.tu-dresden.de
  Lackorzynski         http://os.inf.tu-dresden.de/~adam/