Porting Fiasco+L4re to DaVinci DA850 - prefetch abort in sigma0
Peter Howard
pjh at northern-ridge.com.au
Tue May 13 08:48:58 CEST 2014
Dear all,
I'm trying to port Fiasco to the DA850. I'm basing this on the
2014022818 snapshot. I've gotten to the point where I've modified the
configuration for both fiasco and l4re, added the BSP and bootstrap
platform files, and added the extra drivers I need to get started. I
can build an image to load on the machine and it boots through the
kernel fine. Then it tries to run sigma0 and gets a prefetch abort:
EXCEPTION: prefetch abort pfa=c0090100, error=0033000d
R[0]: c0002000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
R[8]: 00000000 00000000 00000000 00000000 00000000 c1013de4 04080124 c0090100
(note, I'm including the full boot output at the end of the email)
The address, c0090100, is correct as the entry point for sigma0.
Now, if I'm reading the FSR right, that's indicating a permission error
on the section. But nothing I've added/changed has anything to do with
the MMU/mapping. As far as I can see, that's all straight armv5 code,
with nothing special to the board (which uses an arm926ejs core).
So any idea why sigma0 would be getting mappings with the wrong
permission?
------
Full output from boot:
U-Boot > bootm 0xc0700000
## Booting kernel from Legacy Image at c0700000 ...
Image Name: L4 Image #2
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 860160 Bytes = 840 KiB
Load Address: c1000000
Entry Point: c1000000
Verifying Checksum ... OK
Loading Kernel Image ... OK
OK
Starting kernel ...
L4 Bootstrapper
Build: #2 Tue May 13 14:38:28 EST 2014, 4.7.3
Scanning up to 32 MB RAM
Memory size is 32MB (c0000000 - c1ffffff)
RAM: 00000000c0000000 - 00000000c1ffffff: 32768kB
Total RAM: 32MB
mod04: c10b8000-c10d1574: hello
mod03: c109e000-c10b7454: l4re
mod02: c106c000-c109d620: moe
mod01: c1062000-c106b338: sigma0
mod00: c1015000-c1061380: fiasco
Moving up to 5 modules behind c1100000
moving module 00 { c1015000-c106137f } -> { c11bd000-c120937f } [312192]
moving module 01 { c1062000-c106b337 } -> { c120a000-c1213337 } [37688]
moving module 02 { c106c000-c109d61f } -> { c1214000-c124561f } [202272]
moving module 03 { c109e000-c10b7453 } -> { c1100000-c1119453 } [103508]
moving module 04 { c10b8000-c10d1573 } -> { c111a000-c1133573 } [103796]
Scanning fiasco -serial_esc
Scanning sigma0
Scanning moe --init=rom/hello
Relocated mbi to [0xc100e000-0xc100e0e2]
Loading fiasco
Loading sigma0
Loading moe
find kernel info page...
found kernel info page at 0xc0002000
Regions of list 'regions'
[ c0001000, c0001a3f] { a40} Kern fiasco
[ c0002000, c005afff] { 59000} Kern fiasco
[ c0090000, c00965bb] { 65bc} Sigma0 sigma0
[ c0098000, c009e17b] { 617c} Sigma0 sigma0
[ c0140000, c016cb87] { 2cb88} Root moe
[ c0170000, c0186f0f] { 16f10} Root moe
[ c1000000, c10143f3] { 143f4} Boot bootstrap
[ c100a000, c100a0a6] { a7} Boot mbi
[ c100e000, c100e1df] { 1e0} Root Multiboot info
[ c1014048, c101409f] { 58} Boot mbi
[ c1100000, c1133573] { 33574} Root Module
API Version: (87) experimental
Sigma0 config ip:c0090100 sp:c1013de4
Roottask config ip:c0140260 sp:00000000
Starting kernel fiasco at c0001208
Hello from Startup::stage2
Cache config: ON
Timer::Timer()
SERIAL ESC: allocated IRQ 61 for serial uart
Not using serial hack in slow timer handler.
Welcome to Fiasco.OC (arm)!
L4/Fiasco.OC arm microkernel (C) 1998-2013 TU Dresden
Rev: rUnversioned directory compiled with gcc 4.7.3 for Davinci DA850 []
Build: #1 Tue May 13 14:33:35 EST 2014
Calibrating timer loop... done.
MDB: use page size: 20
MDB: use page size: 12
EXCEPTION: prefetch abort pfa=c0090100, error=0033000d
R[0]: c0002000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
R[8]: 00000000 00000000 00000000 00000000 00000000 c1013de4 04080124 c0090100
KERNEL: Warning: Sigma0 raised an exception --> HALT
Panic: ...
Return reboots, "k" enters L4 kernel debugger...
--
Peter Howard <pjh at northern-ridge.com.au>
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