Run and debug Fiasco.OC kernel and L4Re using a DSTREAM JTAG device and the ARM DS-5 IDE
Mahdi Aichouch
foxmehdi at gmail.com
Mon Nov 17 11:39:06 CET 2014
Hello Adam,
Thank you very much for your answer.
I didn't tried yet using an SD card or tftp.
I am interested in testing it using tftp, is there any guide showing how to
setup a working configuration on my development machine?
I compiled the kernel using this command line:
$> make BOOTSTRAP_NO_STRIP=y PLATFORM_UART_NR=1
Now the debugger is not complaining. I have the debug information and I can
also see the source code (as shown in the attached screenshot).
But I still not get the debug information from the kernel in the minicom
serial terminal.
I did a step by step walk through the code, the attached file shows all the
debug information that I get.
Do I used the PLATFORM_UART_NR=1 option correctly, what verification should
I do also?
Thank you very much in advance.
Best regards,
On Sat, Nov 15, 2014 at 10:00 PM, Adam Lackorzynski <
adam at os.inf.tu-dresden.de> wrote:
> Hi,
>
> On Fri Nov 14, 2014 at 15:33:50 +0100, Mahdi Aichouch wrote:
> > I have a Freescale i.MX 6 ARM Cortex A9 Sabre SD board.
> > I would like to test the Hello World example using the generated
> > bootstrap.elf binary.
> > I compiled the fiasco kernel and the l4re framework for the i.MX 6 ARM
> > Cortex-A9 using the menu configuration in both cases.
> >
> > Instead of using an SD card to run the binary on the board, I would like
> to
> > flash the RAM with the binary using the DSTREAM JTAG device and the ARM
> > DS-5 IDE.
> >
> > I connected the board to my host using the mini-usb to serial cable, and
> I
> > used minicom tool as a serial terminal.
> >
> > I tried to run the binary using the DS-5 debugger while the board is
> > connected through JTAG, but I didn't see any debug message on the serial
> > terminal.
>
> Is it working when you boot via SD card or tftp?
>
> > The source code I am using is from the "l4re-snapshot-2014092821".
> >
> > My questions:
> >
> > 1) Does anyone tried to run and debug fiasco kernel + l4re on a board
> using
> > a JTAG device?
> > What are the steps that I am missing?
>
> I've done it, however not with this particular board.
> I don't really think there could be anything missing. The info on the
> screenshot looks ok, the disassembly shows what it has to show.
> Did it stop itself? Or does it run and just no output? When you let it
> run a few seconds and stop it again, at which PC is it?
> Maybe just the wrong UART? UART2 is the default, UART1 would be
> PLATFORM_UART_NR=1
>
> > 2) The debug tool print a message saying that "WARNING(IMG53):
> > bootstrap.elf has no source level debug information", what are the
> options
> > required to include these information compiling the fiasco kernel + l4re?
>
> Add BOOTSTRAP_NO_STRIP=y when building the image (you can also put it
> into your l4/conf/Makeconf.boot).
>
>
>
>
> Adam
> --
> Adam adam at os.inf.tu-dresden.de
> Lackorzynski http://os.inf.tu-dresden.de/~adam/
>
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Stopping running target Freescale - i.MX6 Quad (Generic) on USB:001063 on connection
Connected to running target Freescale - i.MX6 Quad (Generic) on USB:001063
Execution stopped at: S:0x00000FC4
source /v "/home/aichouch/dev/iMX6_Platform_SDK/tools/ds5/MX6Q_SabreSD_DDR3_v1.6.ds"
S:0x00000FC4 BX lr
+stop
WARNING(CMD315): Target is not running
+mem auto
Memory map set to auto
+mem 0x00000000 0xffffffff noverify
Memory table entry number 7 created
+mem set 0x020c4068 32 0xffffffff
+mem set 0x020c406c 32 0xffffffff
+mem set 0x020c4070 32 0xffffffff
+mem set 0x020c4074 32 0xffffffff
+mem set 0x020c4078 32 0xffffffff
+mem set 0x020c407c 32 0xffffffff
+mem set 0x020c4080 32 0xffffffff
+mem set 0x020c4084 32 0xffffffff
+mem set 0x020e0798 32 0x000C0000 # IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
+mem set 0x020e0758 32 0x00000000 # IOMUXC_SW_PAD_CTL_GRP_DDRPKE
+mem set 0x020e0588 32 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
+mem set 0x020e0594 32 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
+mem set 0x020e056c 32 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
+mem set 0x020e0578 32 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
+mem set 0x020e074c 32 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_ADDDS
+mem set 0x020e057c 32 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
+mem set 0x020e058c 32 0x00000000 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS
+mem set 0x020e059c 32 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
+mem set 0x020e05a0 32 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
+mem set 0x020e078c 32 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_CTLDS
+mem set 0x020e0750 32 0x00020000 # IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
+mem set 0x020e05a8 32 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
+mem set 0x020e05b0 32 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
+mem set 0x020e0524 32 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
+mem set 0x020e051c 32 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
+mem set 0x020e0518 32 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4
+mem set 0x020e050c 32 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5
+mem set 0x020e05b8 32 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6
+mem set 0x020e05c0 32 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7
+mem set 0x020e0774 32 0x00020000 # IOMUXC_SW_PAD_CTL_GRP_DDRMODE
+mem set 0x020e0784 32 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_B0DS
+mem set 0x020e0788 32 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_B1DS
+mem set 0x020e0794 32 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_B2DS
+mem set 0x020e079c 32 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_B3DS
+mem set 0x020e07a0 32 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_B4DS
+mem set 0x020e07a4 32 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_B5DS
+mem set 0x020e07a8 32 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_B6DS
+mem set 0x020e0748 32 0x00000030 # IOMUXC_SW_PAD_CTL_GRP_B7DS
+mem set 0x020e05ac 32 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
+mem set 0x020e05b4 32 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
+mem set 0x020e0528 32 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
+mem set 0x020e0520 32 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
+mem set 0x020e0514 32 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4
+mem set 0x020e0510 32 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5
+mem set 0x020e05bc 32 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6
+mem set 0x020e05c4 32 0x00000030 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7
+mem set 0x021b0800 32 0xa1390003 # DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.
+mem set 0x021b080c 32 0x001F001F
+mem set 0x021b0810 32 0x001F001F
+mem set 0x021b480c 32 0x001F001F
+mem set 0x021b4810 32 0x001F001F
+mem set 0x021b083c 32 0x43270338 # MPDGCTRL0 PHY0
+mem set 0x021b0840 32 0x03200314 # MPDGCTRL1 PHY0
+mem set 0x021b483c 32 0x431A032F # MPDGCTRL0 PHY1
+mem set 0x021b4840 32 0x03200263 # MPDGCTRL1 PHY1
+mem set 0x021b0848 32 0x4B434748 # MPRDDLCTL PHY0
+mem set 0x021b4848 32 0x4445404C # MPRDDLCTL PHY1
+mem set 0x021b0850 32 0x38444542 # MPWRDLCTL PHY0
+mem set 0x021b4850 32 0x4935493A # MPWRDLCTL PHY1
+mem set 0x021b081c 32 0x33333333 # DDR_PHY_P0_MPREDQBY0DL3
+mem set 0x021b0820 32 0x33333333 # DDR_PHY_P0_MPREDQBY1DL3
+mem set 0x021b0824 32 0x33333333 # DDR_PHY_P0_MPREDQBY2DL3
+mem set 0x021b0828 32 0x33333333 # DDR_PHY_P0_MPREDQBY3DL3
+mem set 0x021b481c 32 0x33333333 # DDR_PHY_P1_MPREDQBY0DL3
+mem set 0x021b4820 32 0x33333333 # DDR_PHY_P1_MPREDQBY1DL3
+mem set 0x021b4824 32 0x33333333 # DDR_PHY_P1_MPREDQBY2DL3
+mem set 0x021b4828 32 0x33333333 # DDR_PHY_P1_MPREDQBY3DL3
+mem set 0x021b08b8 32 0x00000800 # DDR_PHY_P0_MPMUR0, frc_msr
+mem set 0x021b48b8 32 0x00000800 # DDR_PHY_P0_MPMUR0, frc_msr
+mem set 0x021b0004 32 0x00020036 # MMDC0_MDPDC
+mem set 0x021b0008 32 0x09444040 # MMDC0_MDOTC
+mem set 0x021b000c 32 0x555A7975 # MMDC0_MDCFG0
+mem set 0x021b0010 32 0xFF538F64 # MMDC0_MDCFG1
+mem set 0x021b0014 32 0x01FF00DB # MMDC0_MDCFG2
+mem set 0x021b0018 32 0x00001740 # MMDC0_MDMISC
+mem set 0x021b001c 32 0x00008000 # MMDC0_MDSCR, set the Configuration request bit during MMDC set up
+mem set 0x021b002c 32 0x000026d2 # MMDC0_MDRWD; recommend to maintain the default values
+mem set 0x021b0030 32 0x005A1023 # MMDC0_MDOR
+mem set 0x021b0040 32 0x00000027 # CS0_END
+mem set 0x021b0000 32 0x831A0000 # MMDC0_MDCTL
+mem set 0x021b001c 32 0x04088032 # MMDC0_MDSCR, MR2 write, CS0
+mem set 0x021b001c 32 0x00008033 # MMDC0_MDSCR, MR3 write, CS0
+mem set 0x021b001c 32 0x00048031 # MMDC0_MDSCR, MR1 write, CS0
+mem set 0x021b001c 32 0x09408030 # MMDC0_MDSCR, MR0 write, CS0
+mem set 0x021b001c 32 0x04008040 # MMDC0_MDSCR, ZQ calibration command sent to device on CS0
+mem set 0x021b0020 32 0x00005800 # MMDC0_MDREF
+mem set 0x021b0818 32 0x00011117 # DDR_PHY_P0_MPODTCTRL
+mem set 0x021b4818 32 0x00011117 # DDR_PHY_P1_MPODTCTRL
+mem set 0x021b0004 32 0x00025576 # MMDC0_MDPDC with PWDT bits set
+mem set 0x021b0404 32 0x00011006 # MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.
+mem set 0x021b001c 32 0x00000000 # MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)
loadfile "/home/aichouch/dev/l4re-snapshot-2014092821/obj/l4/arm-ca/images/bootstrap_hello.elf"
Loaded section .text: S:0x11000000 ~ S:0x1100A3EF (size 0xA3F0)
Loaded section .data: S:0x1100B000 ~ S:0x1100F4FF (size 0x4500)
Loaded section .jcr: S:0x1100F500 ~ S:0x1100F503 (size 0x4)
Loaded section .data.m: S:0x11010000 ~ S:0x110EEFFF (size 0xDF000)
Loaded section .ARM.extab: S:0x110EF000 ~ S:0x110EF45B (size 0x45C)
Loaded section .ARM.extab.text._ZN2L49IOBackendD2Ev: S:0x110EF45C ~ S:0x110EF467 (size 0xC)
Loaded section .ARM.extab.text._ZN2L49IOBackendD0Ev: S:0x110EF468 ~ S:0x110EF473 (size 0xC)
Loaded section .ARM.extab.text._ZN13Platform_base6rebootEv: S:0x110EF474 ~ S:0x110EF47F (size 0xC)
Loaded section .ARM.extab.text._ZN13Platform_base17arm_switch_to_hypEv: S:0x110EF480 ~ S:0x110EF48B (size 0xC)
Loaded section .ARM.extab.text._ZN26Platform_single_region_ram7modulesEv: S:0x110EF48C ~ S:0x110EF497 (size 0xC)
Loaded section .ARM.extab.text._ZN26Platform_single_region_ramD2Ev: S:0x110EF498 ~ S:0x110EF4A3 (size 0xC)
Loaded section .ARM.extab.text._ZN26Platform_single_region_ramD0Ev: S:0x110EF4A4 ~ S:0x110EF4AF (size 0xC)
Loaded section .ARM.extab.text._ZN13Platform_base11boot_kernelEm: S:0x110EF4B0 ~ S:0x110EF4BB (size 0xC)
Loaded section .ARM.extab.text._ZN23Boot_modules_image_modeD2Ev: S:0x110EF4BC ~ S:0x110EF4C7 (size 0xC)
Loaded section .ARM.extab.text._ZN23Boot_modules_image_modeD0Ev: S:0x110EF4C8 ~ S:0x110EF4D3 (size 0xC)
Loaded section .ARM.extab.text._ZNK2L422Io_register_block_mmio4addrEm: S:0x110EF4D4 ~ S:0x110EF4DF (size 0xC)
Loaded section .ARM.extab.text._ZNK2L422Io_register_block_mmio5read8Em: S:0x110EF4E0 ~ S:0x110EF4EB (size 0xC)
Loaded section .ARM.extab.text._ZNK2L422Io_register_block_mmio6read16Em: S:0x110EF4EC ~ S:0x110EF4F7 (size 0xC)
Loaded section .ARM.extab.text._ZNK2L422Io_register_block_mmio6read32Em: S:0x110EF4F8 ~ S:0x110EF503 (size 0xC)
Loaded section .ARM.extab.text._ZNK2L422Io_register_block_mmio6write8Emh: S:0x110EF504 ~ S:0x110EF50F (size 0xC)
Loaded section .ARM.extab.text._ZNK2L422Io_register_block_mmio7write16Emt: S:0x110EF510 ~ S:0x110EF51B (size 0xC)
Loaded section .ARM.extab.text._ZNK2L422Io_register_block_mmio7write32Emj: S:0x110EF51C ~ S:0x110EF527 (size 0xC)
Loaded section .ARM.extab.text._ZNK2L422Io_register_block_mmio5delayEv: S:0x110EF528 ~ S:0x110EF533 (size 0xC)
Loaded section .ARM.extab.text._ZN2L44UartD2Ev: S:0x110EF534 ~ S:0x110EF53F (size 0xC)
Loaded section .ARM.extab.text._ZN2L44Uart13enable_rx_irqEb: S:0x110EF540 ~ S:0x110EF54B (size 0xC)
Loaded section .ARM.extab.text._ZN2L422Io_register_block_mmioD2Ev: S:0x110EF54C ~ S:0x110EF557 (size 0xC)
Loaded section .ARM.extab.text._ZN2L410Uart_pl011D2Ev: S:0x110EF558 ~ S:0x110EF563 (size 0xC)
Loaded section .ARM.extab.text._ZN2L44UartD0Ev: S:0x110EF564 ~ S:0x110EF56F (size 0xC)
Loaded section .ARM.extab.text._ZN2L410Uart_pl011D0Ev: S:0x110EF570 ~ S:0x110EF57B (size 0xC)
Loaded section .ARM.extab.text._ZN2L422Io_register_block_mmioD0Ev: S:0x110EF57C ~ S:0x110EF587 (size 0xC)
Loaded section .ARM.extab.text.startup: S:0x110EF588 ~ S:0x110EF593 (size 0xC)
Loaded section .ARM.extab.text._ZN13Platform_base17iterate_platformsEv: S:0x110EF594 ~ S:0x110EF59F (size 0xC)
Entry point S:0x11000000
cd "/home/aichouch/DS-5-Workspace-examples"
Working directory "/home/aichouch/DS-5-Workspace-examples"
directory "/home/aichouch/dev/l4re-snapshot-2014092821/src/kernel/fiasco/src"
Source directories searched: /home/aichouch/dev/l4re-snapshot-2014092821/src/kernel/fiasco/src:$cdir:$cwd:$idir
directory "/home/aichouch/dev/l4re-snapshot-2014092821/src/kernel/fiasco/src" "/home/aichouch/dev/l4re-snapshot-2014092821/src/l4/pkg"
Source directories searched: /home/aichouch/dev/l4re-snapshot-2014092821/src/kernel/fiasco/src:/home/aichouch/dev/l4re-snapshot-2014092821/src/l4/pkg:$cdir:$cwd:$idir
set debug-from main
start
Starting target with image /home/aichouch/dev/l4re-snapshot-2014092821/obj/l4/arm-ca/pkg/bootstrap/server/src/OBJ-arm_armv7a/bootstrap.elf
Running from entry point
WARNING(CMD399-COR168):
! Failed to start the target
! No function named "main" could be found
WARNING(CMD407): Trying the entry point instead
wait
Execution stopped at: S:0x11000000
In crt0.S
S:0x11000000 20,0 nop
wait
next
Execution stopped at: S:0x11000004
S:0x11000004 21,0 nop
wait
next
Execution stopped at: S:0x11000008
S:0x11000008 22,0 nop
wait
next
Execution stopped at: S:0x1100000C
S:0x1100000C 23,0 nop
wait
next
Execution stopped at: S:0x11000010
S:0x11000010 24,0 nop
wait
next
Execution stopped at: S:0x11000014
S:0x11000014 25,0 nop
wait
next
Execution stopped at: S:0x11000018
S:0x11000018 26,0 nop
wait
next
Execution stopped at: S:0x1100001C
S:0x1100001C 27,0 nop
wait
next
Execution stopped at: S:0x11000020
S:0x11000020 28,0 b 10f
wait
next
Execution stopped at: S:0x11000030
S:0x11000030 39,0 adr r4, run /* Running version */
wait
next
Execution stopped at: S:0x11000034
S:0x11000034 40,0 ldr r5, .LCrun /* supposed to be version */
wait
next
Execution stopped at: S:0x11000038
S:0x11000038 41,0 cmp r4, r5 /* If equal ... */
wait
next
Execution stopped at: S:0x1100003C
S:0x1100003C 42,0 beq run /* ... go to run */
wait
next
Execution stopped at: S:0x110000CC
S:0x110000CC 94,0 mov r3, #0x1000
wait
next
Execution stopped at: S:0x110000D0
S:0x110000D0 95,0 sub r3, r3, #1 /* r3 == 0xfff */
wait
next
Execution stopped at: S:0x110000D4
S:0x110000D4 96,0 mrc p15, 0, r0, c0, c0, 0 /* Main ID */
wait
next
Execution stopped at: S:0x110000D8
S:0x110000D8 97,0 lsr r0, #4
wait
next
Execution stopped at: S:0x110000DC
S:0x110000DC 98,0 and r0, r0, r3
wait
next
Execution stopped at: S:0x110000E0
S:0x110000E0 101,0 mov r9, #0xb00
wait
next
Execution stopped at: S:0x110000E4
S:0x110000E4 102,0 orr r9, #0x002
wait
next
Execution stopped at: S:0x110000E8
S:0x110000E8 103,0 cmp r0, r9
wait
next
Execution stopped at: S:0x110000EC
S:0x110000EC 104,0 beq do_cpuid
wait
next
Execution stopped at: S:0x110000F0
S:0x110000F0 106,0 mov r3, #0xc00
wait
next
Execution stopped at: S:0x110000F4
S:0x110000F4 107,0 orr r9, r3, #0x00f
wait
next
Execution stopped at: S:0x110000F8
S:0x110000F8 108,0 cmp r0, r9
wait
next
Execution stopped at: S:0x110000FC
S:0x110000FC 109,0 beq do_cpuid
wait
next
Execution stopped at: S:0x11000100
S:0x11000100 111,0 orr r9, r3, #0x007
wait
next
Execution stopped at: S:0x11000104
S:0x11000104 112,0 cmp r0, r9
wait
next
Execution stopped at: S:0x11000108
S:0x11000108 113,0 beq do_cpuid
wait
next
Execution stopped at: S:0x1100010C
S:0x1100010C 115,0 orr r9, r3, #0x009
wait
next
Execution stopped at: S:0x11000110
S:0x11000110 116,0 cmp r0, r9
wait
next
Execution stopped at: S:0x11000114
S:0x11000114 117,0 bne do_bootstrap /* None matched, normal startup */
wait
next
Execution stopped at: S:0x11000118
S:0x11000118 120,0 mrc p15, 0, r0, c0, c0, 5 /* CPU ID */
wait
next
Execution stopped at: S:0x1100011C
S:0x1100011C 121,0 and r0, r0, #0xf /* CPU id */
wait
next
Execution stopped at: S:0x11000120
S:0x11000120 122,0 cmp r0, #0 /* CPU0 continues with bootstrap */
wait
next
Execution stopped at: S:0x11000124
S:0x11000124 123,0 beq do_bootstrap
wait
next
Execution stopped at: S:0x110001E8
S:0x110001E8 206,0 ldr r3, .LCcrt0_tramppage /* Load address of tramppage var */
wait
next
Execution stopped at: S:0x110001EC
S:0x110001EC 207,0 str sp, [r3] /* Store SP in variable */
wait
next
Execution stopped at: S:0x110001F0
S:0x110001F0 208,0 ldr sp, .LCstack
wait
next
Execution stopped at: S:0x110001F4
S:0x110001F4 210,0 mov r0, r2 /* ATAG pointer */
wait
next
Execution stopped at: S:0x110001F8
S:0x110001F8 211,0 bl __main
wait
next
interrupt
Execution stopped at: S:0x11003844
In io_regblock.h
S:0x11003844 187,0 unsigned int read32(unsigned long reg) const
wait
continue
interrupt
Execution stopped at: S:0x11003E2C
In poll_timeout_counter.h
S:0x11003E2C 28,0 if (!expression)
wait
continue
interrupt
Execution stopped at: S:0x11003E78
S:0x11003E78 28,0 if (!expression)
wait
continue
interrupt
Execution stopped at: S:0x11003E78
S:0x11003E78 28,0 if (!expression)
wait
continue
interrupt
Execution stopped at: S:0x11003844
In io_regblock.h
S:0x11003844 187,0 unsigned int read32(unsigned long reg) const
wait
continue
interrupt
Execution stopped at: S:0x11003844
S:0x11003844 187,0 unsigned int read32(unsigned long reg) const
wait
continue
interrupt
Execution stopped at: S:0x11003E80
In poll_timeout_counter.h
S:0x11003E80 31,0 if (_c)
wait
continue
interrupt
Execution stopped at: S:0x11003844
In io_regblock.h
S:0x11003844 187,0 unsigned int read32(unsigned long reg) const
wait
continue
interrupt
Execution stopped at: S:0x11003E80
In poll_timeout_counter.h
S:0x11003E80 31,0 if (_c)
wait
next
Execution stopped at: S:0x11003E64
In uart_pl011.cc
S:0x11003E64 139,0 while (i.test(_regs->read<unsigned int>(UART01x_FR) & UART01x_FR_BUSY))
wait
next
Execution stopped at: S:0x11003E78
In poll_timeout_counter.h
S:0x11003E78 28,0 if (!expression)
wait
next
Execution stopped at: S:0x11003E80
S:0x11003E80 31,0 if (_c)
wait
next
Execution stopped at: S:0x11003E64
In uart_pl011.cc
S:0x11003E64 139,0 while (i.test(_regs->read<unsigned int>(UART01x_FR) & UART01x_FR_BUSY))
wait
next
Execution stopped at: S:0x11003E78
In poll_timeout_counter.h
S:0x11003E78 28,0 if (!expression)
wait
next
Execution stopped at: S:0x11003E80
S:0x11003E80 31,0 if (_c)
wait
next
Execution stopped at: S:0x11003E64
In uart_pl011.cc
S:0x11003E64 139,0 while (i.test(_regs->read<unsigned int>(UART01x_FR) & UART01x_FR_BUSY))
wait
next
Execution stopped at: S:0x11003E78
In poll_timeout_counter.h
S:0x11003E78 28,0 if (!expression)
wait
next
Execution stopped at: S:0x11003E80
S:0x11003E80 31,0 if (_c)
wait
next
Execution stopped at: S:0x11003E64
In uart_pl011.cc
S:0x11003E64 139,0 while (i.test(_regs->read<unsigned int>(UART01x_FR) & UART01x_FR_BUSY))
wait
next
Execution stopped at: S:0x11003E78
In poll_timeout_counter.h
S:0x11003E78 28,0 if (!expression)
wait
next
Execution stopped at: S:0x11003E80
S:0x11003E80 31,0 if (_c)
wait
continue
interrupt
Execution stopped at: S:0x11003E2C
S:0x11003E2C 28,0 if (!expression)
wait
next
Execution stopped at: S:0x11003E34
S:0x11003E34 31,0 if (_c)
wait
next
Execution stopped at: S:0x11003E18
In uart_pl011.cc
S:0x11003E18 127,0 while (i.test(_regs->read<unsigned int>(UART01x_FR) & UART01x_FR_TXFF))
wait
next
Execution stopped at: S:0x11003E2C
In poll_timeout_counter.h
S:0x11003E2C 28,0 if (!expression)
wait
next
Execution stopped at: S:0x11003E34
S:0x11003E34 31,0 if (_c)
wait
next
Execution stopped at: S:0x11003E18
In uart_pl011.cc
S:0x11003E18 127,0 while (i.test(_regs->read<unsigned int>(UART01x_FR) & UART01x_FR_TXFF))
wait
finish
Execution stopped at: S:0x11003E54
S:0x11003E54 135,0 while (c--)
wait
next
Execution stopped at: S:0x11003E5C
S:0x11003E5C 136,0 out_char(*s++);
wait
next
Execution stopped at: S:0x11003E64
S:0x11003E64 139,0 while (i.test(_regs->read<unsigned int>(UART01x_FR) & UART01x_FR_BUSY))
wait
next
Execution stopped at: S:0x11003E78
In poll_timeout_counter.h
S:0x11003E78 28,0 if (!expression)
wait
next
Execution stopped at: S:0x11003E80
S:0x11003E80 31,0 if (_c)
wait
next
Execution stopped at: S:0x11003E64
In uart_pl011.cc
S:0x11003E64 139,0 while (i.test(_regs->read<unsigned int>(UART01x_FR) & UART01x_FR_BUSY))
wait
next
Execution stopped at: S:0x11003E78
In poll_timeout_counter.h
S:0x11003E78 28,0 if (!expression)
wait
next
Execution stopped at: S:0x11003E80
S:0x11003E80 31,0 if (_c)
wait
next
Execution stopped at: S:0x11003E64
In uart_pl011.cc
S:0x11003E64 139,0 while (i.test(_regs->read<unsigned int>(UART01x_FR) & UART01x_FR_BUSY))
wait
next
Execution stopped at: S:0x11003E78
In poll_timeout_counter.h
S:0x11003E78 28,0 if (!expression)
wait
continue
interrupt
Execution stopped at: S:0x11003E78
S:0x11003E78 28,0 if (!expression)
wait
continue
interrupt
Execution stopped at: S:0x11003844
In io_regblock.h
S:0x11003844 187,0 unsigned int read32(unsigned long reg) const
wait
continue
interrupt
Execution stopped at: S:0x11003E68
S:0x11003E68 91,0 case 4: return read32(reg);
wait
continue
interrupt
Execution stopped at: S:0x11003844
S:0x11003844 187,0 unsigned int read32(unsigned long reg) const
wait
continue
interrupt
Execution stopped at: S:0x11003E2C
In poll_timeout_counter.h
S:0x11003E2C 28,0 if (!expression)
wait
continue
interrupt
Execution stopped at: S:0x11003844
In io_regblock.h
S:0x11003844 187,0 unsigned int read32(unsigned long reg) const
wait
continue
interrupt
Execution stopped at: S:0x11003844
S:0x11003844 187,0 unsigned int read32(unsigned long reg) const
wait
continue
interrupt
Execution stopped at: S:0x11003844
S:0x11003844 187,0 unsigned int read32(unsigned long reg) const
wait
continue
interrupt
Execution stopped at: S:0x11003E2C
In poll_timeout_counter.h
S:0x11003E2C 28,0 if (!expression)
wait
continue
interrupt
Execution stopped at: S:0x11003844
In io_regblock.h
S:0x11003844 187,0 unsigned int read32(unsigned long reg) const
wait
continue
interrupt
Execution stopped at: S:0x11003E78
In poll_timeout_counter.h
S:0x11003E78 28,0 if (!expression)
wait
step
Execution stopped at: S:0x11003E80
S:0x11003E80 31,0 if (_c)
wait
next
Execution stopped at: S:0x11003E64
In uart_pl011.cc
S:0x11003E64 139,0 while (i.test(_regs->read<unsigned int>(UART01x_FR) & UART01x_FR_BUSY))
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