Run and debug Fiasco.OC kernel and L4Re using a DSTREAM JTAG device and the ARM DS-5 IDE

[Adam Lackorzynski]

Hi,

On Fri Nov 14, 2014 at 15:33:50 +0100, Mahdi Aichouch wrote:
> I have a Freescale i.MX 6 ARM Cortex A9 Sabre SD board.
> I would like to test the Hello World example using the generated
> bootstrap.elf binary.
> I compiled the fiasco kernel and the l4re framework for the i.MX 6 ARM
> Cortex-A9 using the menu configuration in both cases.
> 
> Instead of using an SD card to run the binary on the board, I would like to
> flash the RAM with the binary using the DSTREAM JTAG device and the ARM
> DS-5 IDE.
> 
> I connected the board to my host using the mini-usb to serial cable, and I
> used minicom tool as a serial terminal.
> 
> I tried to run the binary using the DS-5 debugger while the board is
> connected through JTAG, but I didn't see any debug message on the serial
> terminal.

Is it working when you boot via SD card or tftp?

> The source code I am using is from the "l4re-snapshot-2014092821".
> 
> My questions:
> 
> 1) Does anyone tried to run and debug fiasco kernel + l4re on a board using
> a JTAG device?
> What are the steps that I am missing?

I've done it, however not with this particular board.
I don't really think there could be anything missing. The info on the
screenshot looks ok, the disassembly shows what it has to show.
Did it stop itself? Or does it run and just no output? When you let it
run a few seconds and stop it again, at which PC is it?
Maybe just the wrong UART? UART2 is the default, UART1 would be
PLATFORM_UART_NR=1

> 2) The debug tool print a message saying that "WARNING(IMG53):
> bootstrap.elf has no source level debug information", what are the options
> required to include these information compiling the fiasco kernel + l4re?

Add BOOTSTRAP_NO_STRIP=y when building the image (you can also put it
into your l4/conf/Makeconf.boot).




Adam
-- 
Adam                 adam at os.inf.tu-dresden.de
  Lackorzynski         http://os.inf.tu-dresden.de/~adam/