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vbus_pci
// vi:set ft=cpp: -*- Mode: C++ -*-
/*
* (c) 2014 Sarah Hoffmann <sarah.hoffmann@kernkonzept.com>
*
* License: see LICENSE.spdx (in this directory or the directories above)
*/
#pragma once
#include <l4/vbus/vbus>
#include <l4/vbus/vbus_pci.h>
namespace L4vbus {
class Pci_host_bridge : public Device
{
public:
int cfg_read(l4_uint32_t bus, l4_uint32_t devfn, l4_uint32_t reg,
l4_uint32_t *value, l4_uint32_t width) const
{
return l4vbus_pci_cfg_read(bus_cap().cap(), _dev, bus,
devfn, reg, value, width);
}
int cfg_write(l4_uint32_t bus, l4_uint32_t devfn, l4_uint32_t reg,
l4_uint32_t value, l4_uint32_t width) const
{
return l4vbus_pci_cfg_write(bus_cap().cap(), _dev, bus,
devfn, reg, value, width);
}
int irq_enable(l4_uint32_t bus, l4_uint32_t devfn, int pin,
unsigned char *trigger, unsigned char *polarity) const
{
return l4vbus_pci_irq_enable(bus_cap().cap(), _dev, bus,
devfn, pin, trigger, polarity);
}
};
class Pci_dev : public Device
{
public:
int cfg_read(l4_uint32_t reg, l4_uint32_t *value,
l4_uint32_t width) const
{
return l4vbus_pcidev_cfg_read(bus_cap().cap(), _dev, reg, value, width);
}
int cfg_write(l4_uint32_t reg, l4_uint32_t value,
l4_uint32_t width) const
{
return l4vbus_pcidev_cfg_write(bus_cap().cap(), _dev, reg, value, width);
}
int irq_enable(unsigned char *trigger, unsigned char *polarity) const
{
return l4vbus_pcidev_irq_enable(bus_cap().cap(), _dev, trigger, polarity);
}
};
}
L4vbus::Device::bus_cap
L4::Cap< Vbus > bus_cap() const
Access the Vbus capability of the underlying virtual bus.
Definition vbus:107
L4vbus::Device::Device
Device()
Construct a new vbus device using the NULL device L4VBUS_NULL.
Definition vbus:89
L4vbus::Device::_dev
l4vbus_device_handle_t _dev
The device handle for this device.
Definition vbus:247
L4vbus::Pci_dev
A PCI device.
Definition vbus_pci:94
L4vbus::Pci_dev::cfg_write
int cfg_write(l4_uint32_t reg, l4_uint32_t value, l4_uint32_t width) const
Write to the device's vPCI configuration space.
Definition vbus_pci:121
L4vbus::Pci_dev::cfg_read
int cfg_read(l4_uint32_t reg, l4_uint32_t *value, l4_uint32_t width) const
Read from the device's vPCI configuration space.
Definition vbus_pci:105
L4vbus::Pci_dev::irq_enable
int irq_enable(unsigned char *trigger, unsigned char *polarity) const
Enable the device's PCI interrupt.
Definition vbus_pci:137
L4vbus::Pci_host_bridge
A Pci host bridge.
Definition vbus_pci:26
L4vbus::Pci_host_bridge::cfg_read
int cfg_read(l4_uint32_t bus, l4_uint32_t devfn, l4_uint32_t reg, l4_uint32_t *value, l4_uint32_t width) const
Read from the vPCI configuration space using the PCI root bridge.
Definition vbus_pci:39
L4vbus::Pci_host_bridge::irq_enable
int irq_enable(l4_uint32_t bus, l4_uint32_t devfn, int pin, unsigned char *trigger, unsigned char *polarity) const
Enable PCI interrupt for a specific device using the PCI root bridge.
Definition vbus_pci:79
L4vbus::Pci_host_bridge::cfg_write
int cfg_write(l4_uint32_t bus, l4_uint32_t devfn, l4_uint32_t reg, l4_uint32_t value, l4_uint32_t width) const
Write to the vPCI configuration space using the PCI root bridge.
Definition vbus_pci:58
l4_uint32_t
unsigned int l4_uint32_t
Unsigned 32bit value.
Definition l4int.h:29
l4vbus_pci_cfg_read
L4_BEGIN_DECLS int l4vbus_pci_cfg_read(l4_cap_idx_t vbus, l4vbus_device_handle_t handle, l4_uint32_t bus, l4_uint32_t devfn, l4_uint32_t reg, l4_uint32_t *value, l4_uint32_t width)
Read from the vPCI configuration space using the PCI root bridge.
l4vbus_pci_cfg_write
int l4vbus_pci_cfg_write(l4_cap_idx_t vbus, l4vbus_device_handle_t handle, l4_uint32_t bus, l4_uint32_t devfn, l4_uint32_t reg, l4_uint32_t value, l4_uint32_t width)
Write to the vPCI configuration space using the PCI root bridge.
l4vbus_pcidev_irq_enable
int l4vbus_pcidev_irq_enable(l4_cap_idx_t vbus, l4vbus_device_handle_t handle, unsigned char *trigger, unsigned char *polarity)
Enable the device's PCI interrupt.
l4vbus_pci_irq_enable
int l4vbus_pci_irq_enable(l4_cap_idx_t vbus, l4vbus_device_handle_t handle, l4_uint32_t bus, l4_uint32_t devfn, int pin, unsigned char *trigger, unsigned char *polarity)
Enable PCI interrupt for a specific device using the PCI root bridge.
l4vbus_pcidev_cfg_write
int l4vbus_pcidev_cfg_write(l4_cap_idx_t vbus, l4vbus_device_handle_t handle, l4_uint32_t reg, l4_uint32_t value, l4_uint32_t width)
Write to the device's vPCI configuration space.
l4vbus_pcidev_cfg_read
int l4vbus_pcidev_cfg_read(l4_cap_idx_t vbus, l4vbus_device_handle_t handle, l4_uint32_t reg, l4_uint32_t *value, l4_uint32_t width)
Read from the device's vPCI configuration space.
L4vbus
C++ interface of the Vbus API.
Definition vbus:40