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l4re-base-25.08.0

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This commit is contained in:
Viktor Reusch
2025-09-12 15:55:45 +02:00
commit d959eaab98
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doc/source/html/annotated_dup.js Normal file
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@@ -0,0 +1,449 @@
var annotated_dup =
[
[ "cxx", "namespacecxx.html", [
[ "arith", null, [
[ "Ld", "structcxx_1_1arith_1_1Ld.html", null ]
] ],
[ "Bits", "namespacecxx_1_1Bits.html", [
[ "Avl_map_get_key", "structcxx_1_1Bits_1_1Avl__map__get__key.html", null ],
[ "Avl_set_get_key", "structcxx_1_1Bits_1_1Avl__set__get__key.html", null ],
[ "Base_avl_set", "classcxx_1_1Bits_1_1Base__avl__set.html", "classcxx_1_1Bits_1_1Base__avl__set" ],
[ "Bst", "classcxx_1_1Bits_1_1Bst.html", "classcxx_1_1Bits_1_1Bst" ],
[ "Direction", "structcxx_1_1Bits_1_1Direction.html", "structcxx_1_1Bits_1_1Direction" ],
[ "Bst_node", "classcxx_1_1Bits_1_1Bst__node.html", "classcxx_1_1Bits_1_1Bst__node" ],
[ "Basic_list", "classcxx_1_1Bits_1_1Basic__list.html", "classcxx_1_1Bits_1_1Basic__list" ],
[ "Smart_ptr_list_item", "classcxx_1_1Bits_1_1Smart__ptr__list__item.html", null ],
[ "Smart_ptr_list", "classcxx_1_1Bits_1_1Smart__ptr__list.html", "classcxx_1_1Bits_1_1Smart__ptr__list" ]
] ],
[ "Avl_map", "classcxx_1_1Avl__map.html", "classcxx_1_1Avl__map" ],
[ "Avl_set", "classcxx_1_1Avl__set.html", null ],
[ "Avl_tree_node", "classcxx_1_1Avl__tree__node.html", "classcxx_1_1Avl__tree__node" ],
[ "Avl_tree", "classcxx_1_1Avl__tree.html", "classcxx_1_1Avl__tree" ],
[ "Bitfield", "classcxx_1_1Bitfield.html", "classcxx_1_1Bitfield" ],
[ "Bitmap_base", "classcxx_1_1Bitmap__base.html", "classcxx_1_1Bitmap__base" ],
[ "Bitmap", "classcxx_1_1Bitmap.html", "classcxx_1_1Bitmap" ],
[ "H_list_item_t", "classcxx_1_1H__list__item__t.html", "classcxx_1_1H__list__item__t" ],
[ "H_list", "classcxx_1_1H__list.html", "classcxx_1_1H__list" ],
[ "H_list_t", "structcxx_1_1H__list__t.html", null ],
[ "List_item", "classcxx_1_1List__item.html", "classcxx_1_1List__item" ],
[ "List", "classcxx_1_1List.html", "classcxx_1_1List" ],
[ "List_alloc", "classcxx_1_1List__alloc.html", "classcxx_1_1List__alloc" ],
[ "Pair", "structcxx_1_1Pair.html", "structcxx_1_1Pair" ],
[ "Pair_first_compare", "classcxx_1_1Pair__first__compare.html", "classcxx_1_1Pair__first__compare" ],
[ "Ref_ptr", "classcxx_1_1Ref__ptr.html", "classcxx_1_1Ref__ptr" ],
[ "Ref_obj_list_item", "structcxx_1_1Ref__obj__list__item.html", null ],
[ "Base_slab", "classcxx_1_1Base__slab.html", "classcxx_1_1Base__slab" ],
[ "Slab", "classcxx_1_1Slab.html", "classcxx_1_1Slab" ],
[ "Base_slab_static", "classcxx_1_1Base__slab__static.html", "classcxx_1_1Base__slab__static" ],
[ "Slab_static", "classcxx_1_1Slab__static.html", "classcxx_1_1Slab__static" ],
[ "S_list", "classcxx_1_1S__list.html", "classcxx_1_1S__list" ],
[ "static_vector", "classcxx_1_1static__vector.html", "classcxx_1_1static__vector" ],
[ "Nothrow", "classcxx_1_1Nothrow.html", null ],
[ "New_allocator", "classcxx_1_1New__allocator.html", null ],
[ "Lt_functor", "structcxx_1_1Lt__functor.html", null ],
[ "String", "classcxx_1_1String.html", "classcxx_1_1String" ],
[ "Weak_ref_base", "classcxx_1_1Weak__ref__base.html", "classcxx_1_1Weak__ref__base" ],
[ "Weak_ref", "classcxx_1_1Weak__ref.html", null ]
] ],
[ "L4", "namespaceL4.html", [
[ "Typeid", "namespaceL4_1_1Typeid.html", [
[ "Detail", null, [
[ "Rpcs_end", "structL4_1_1Typeid_1_1Detail_1_1Rpcs__end.html", null ],
[ "_Rpcs", "structL4_1_1Typeid_1_1Detail_1_1__Rpcs.html", null ],
[ "_Rpcs< OPCODE, O, R, X... >", "structL4_1_1Typeid_1_1Detail_1_1__Rpcs_3_01OPCODE_00_01O_00_01R_00_01X_8_8_8_01_4.html", "structL4_1_1Typeid_1_1Detail_1_1__Rpcs_3_01OPCODE_00_01O_00_01R_00_01X_8_8_8_01_4" ]
] ],
[ "P_dispatch", "structL4_1_1Typeid_1_1P__dispatch.html", null ],
[ "Raw_ipc", "structL4_1_1Typeid_1_1Raw__ipc.html", null ],
[ "Rpcs", "structL4_1_1Typeid_1_1Rpcs.html", null ],
[ "Rpcs_code", "structL4_1_1Typeid_1_1Rpcs__code.html", "structL4_1_1Typeid_1_1Rpcs__code" ],
[ "Rpc_nocode", "structL4_1_1Typeid_1_1Rpc__nocode.html", null ],
[ "Rpcs_sys", "structL4_1_1Typeid_1_1Rpcs__sys.html", null ]
] ],
[ "Ipc", "namespaceL4_1_1Ipc.html", [
[ "Msg", "namespaceL4_1_1Ipc_1_1Msg.html", [
[ "Elem< Array< A, LEN > >", "structL4_1_1Ipc_1_1Msg_1_1Elem_3_01Array_3_01A_00_01LEN_01_4_01_4.html", "structL4_1_1Ipc_1_1Msg_1_1Elem_3_01Array_3_01A_00_01LEN_01_4_01_4" ],
[ "Elem< Array< A, LEN > & >", "structL4_1_1Ipc_1_1Msg_1_1Elem_3_01Array_3_01A_00_01LEN_01_4_01_6_01_4.html", "structL4_1_1Ipc_1_1Msg_1_1Elem_3_01Array_3_01A_00_01LEN_01_4_01_6_01_4" ],
[ "Elem< Array_ref< A, LEN > & >", "structL4_1_1Ipc_1_1Msg_1_1Elem_3_01Array__ref_3_01A_00_01LEN_01_4_01_6_01_4.html", "structL4_1_1Ipc_1_1Msg_1_1Elem_3_01Array__ref_3_01A_00_01LEN_01_4_01_6_01_4" ],
[ "Dir_in", "structL4_1_1Ipc_1_1Msg_1_1Dir__in.html", null ],
[ "Dir_out", "structL4_1_1Ipc_1_1Msg_1_1Dir__out.html", null ],
[ "Cls_data", "structL4_1_1Ipc_1_1Msg_1_1Cls__data.html", null ],
[ "Cls_item", "structL4_1_1Ipc_1_1Msg_1_1Cls__item.html", null ],
[ "Cls_buffer", "structL4_1_1Ipc_1_1Msg_1_1Cls__buffer.html", null ],
[ "Do_in_data", "structL4_1_1Ipc_1_1Msg_1_1Do__in__data.html", null ],
[ "Do_out_data", "structL4_1_1Ipc_1_1Msg_1_1Do__out__data.html", null ],
[ "Do_in_items", "structL4_1_1Ipc_1_1Msg_1_1Do__in__items.html", null ],
[ "Do_out_items", "structL4_1_1Ipc_1_1Msg_1_1Do__out__items.html", null ],
[ "Do_rcv_buffers", "structL4_1_1Ipc_1_1Msg_1_1Do__rcv__buffers.html", null ],
[ "Svr_val_ops", "structL4_1_1Ipc_1_1Msg_1_1Svr__val__ops.html", null ],
[ "Is_valid_rpc_type", "structL4_1_1Ipc_1_1Msg_1_1Is__valid__rpc__type.html", null ],
[ "Svr_arg_pack", "structL4_1_1Ipc_1_1Msg_1_1Svr__arg__pack.html", null ],
[ "True", "structL4_1_1Ipc_1_1Msg_1_1True.html", null ],
[ "False", "structL4_1_1Ipc_1_1Msg_1_1False.html", null ]
] ],
[ "Array_ref", "structL4_1_1Ipc_1_1Array__ref.html", null ],
[ "Array", "structL4_1_1Ipc_1_1Array.html", "structL4_1_1Ipc_1_1Array" ],
[ "Array_in_buf", "structL4_1_1Ipc_1_1Array__in__buf.html", "structL4_1_1Ipc_1_1Array__in__buf" ],
[ "Call", "structL4_1_1Ipc_1_1Call.html", null ],
[ "Call_zero_send_timeout", "structL4_1_1Ipc_1_1Call__zero__send__timeout.html", null ],
[ "Call_t", "structL4_1_1Ipc_1_1Call__t.html", null ],
[ "Send_only", "structL4_1_1Ipc_1_1Send__only.html", null ],
[ "Ret_array", "structL4_1_1Ipc_1_1Ret__array.html", null ],
[ "Out", "structL4_1_1Ipc_1_1Out.html", null ],
[ "In_out", "structL4_1_1Ipc_1_1In__out.html", null ],
[ "As_value", "structL4_1_1Ipc_1_1As__value.html", null ],
[ "Opt", "structL4_1_1Ipc_1_1Opt.html", "structL4_1_1Ipc_1_1Opt" ],
[ "Small_buf", "classL4_1_1Ipc_1_1Small__buf.html", "classL4_1_1Ipc_1_1Small__buf" ],
[ "Gen_fpage", "classL4_1_1Ipc_1_1Gen__fpage.html", "classL4_1_1Ipc_1_1Gen__fpage" ],
[ "Snd_fpage", "classL4_1_1Ipc_1_1Snd__fpage.html", "classL4_1_1Ipc_1_1Snd__fpage" ],
[ "Rcv_fpage", "classL4_1_1Ipc_1_1Rcv__fpage.html", "classL4_1_1Ipc_1_1Rcv__fpage" ],
[ "Cap", "classL4_1_1Ipc_1_1Cap.html", "classL4_1_1Ipc_1_1Cap" ],
[ "Varg", "classL4_1_1Ipc_1_1Varg.html", "classL4_1_1Ipc_1_1Varg" ],
[ "Varg_list", "classL4_1_1Ipc_1_1Varg__list.html", "classL4_1_1Ipc_1_1Varg__list" ],
[ "Varg_list_ref", "classL4_1_1Ipc_1_1Varg__list__ref.html", "classL4_1_1Ipc_1_1Varg__list__ref" ],
[ "Str_cp_in", "classL4_1_1Ipc_1_1Str__cp__in.html", "classL4_1_1Ipc_1_1Str__cp__in" ],
[ "Msg_ptr", "classL4_1_1Ipc_1_1Msg__ptr.html", "classL4_1_1Ipc_1_1Msg__ptr" ],
[ "Istream", "classL4_1_1Ipc_1_1Istream.html", "classL4_1_1Ipc_1_1Istream" ],
[ "Ostream", "classL4_1_1Ipc_1_1Ostream.html", "classL4_1_1Ipc_1_1Ostream" ],
[ "Iostream", "classL4_1_1Ipc_1_1Iostream.html", "classL4_1_1Ipc_1_1Iostream" ]
] ],
[ "Ipc_svr", "namespaceL4_1_1Ipc__svr.html", [
[ "Server_iface", "classL4_1_1Ipc__svr_1_1Server__iface.html", "classL4_1_1Ipc__svr_1_1Server__iface" ],
[ "Ignore_errors", "structL4_1_1Ipc__svr_1_1Ignore__errors.html", null ],
[ "Default_timeout", "structL4_1_1Ipc__svr_1_1Default__timeout.html", null ],
[ "Compound_reply", "structL4_1_1Ipc__svr_1_1Compound__reply.html", null ],
[ "Default_setup_wait", "structL4_1_1Ipc__svr_1_1Default__setup__wait.html", null ],
[ "Direct_dispatch", "structL4_1_1Ipc__svr_1_1Direct__dispatch.html", "structL4_1_1Ipc__svr_1_1Direct__dispatch" ],
[ "Direct_dispatch< R * >", "structL4_1_1Ipc__svr_1_1Direct__dispatch_3_01R_01_5_01_4.html", "structL4_1_1Ipc__svr_1_1Direct__dispatch_3_01R_01_5_01_4" ],
[ "Exc_dispatch", "structL4_1_1Ipc__svr_1_1Exc__dispatch.html", "structL4_1_1Ipc__svr_1_1Exc__dispatch" ],
[ "Dbg_dispatch", "structL4_1_1Ipc__svr_1_1Dbg__dispatch.html", "structL4_1_1Ipc__svr_1_1Dbg__dispatch" ],
[ "Br_manager_no_buffers", "classL4_1_1Ipc__svr_1_1Br__manager__no__buffers.html", "classL4_1_1Ipc__svr_1_1Br__manager__no__buffers" ],
[ "Default_loop_hooks", "structL4_1_1Ipc__svr_1_1Default__loop__hooks.html", null ],
[ "Timeout", "classL4_1_1Ipc__svr_1_1Timeout.html", "classL4_1_1Ipc__svr_1_1Timeout" ],
[ "Timeout_queue", "classL4_1_1Ipc__svr_1_1Timeout__queue.html", "classL4_1_1Ipc__svr_1_1Timeout__queue" ],
[ "Timeout_queue_hooks", "classL4_1_1Ipc__svr_1_1Timeout__queue__hooks.html", "classL4_1_1Ipc__svr_1_1Timeout__queue__hooks" ]
] ],
[ "Types", "namespaceL4_1_1Types.html", [
[ "Flags", "classL4_1_1Types_1_1Flags.html", "classL4_1_1Types_1_1Flags" ],
[ "Int_for_size", "structL4_1_1Types_1_1Int__for__size.html", null ],
[ "Int_for_type", "structL4_1_1Types_1_1Int__for__type.html", "structL4_1_1Types_1_1Int__for__type" ],
[ "Flags_ops_t", "structL4_1_1Types_1_1Flags__ops__t.html", "structL4_1_1Types_1_1Flags__ops__t" ],
[ "Flags_t", "structL4_1_1Types_1_1Flags__t.html", "structL4_1_1Types_1_1Flags__t" ],
[ "Bool", "structL4_1_1Types_1_1Bool.html", "structL4_1_1Types_1_1Bool" ],
[ "False", "structL4_1_1Types_1_1False.html", null ],
[ "True", "structL4_1_1Types_1_1True.html", null ],
[ "Same", "structL4_1_1Types_1_1Same.html", null ]
] ],
[ "Kip", null, [
[ "Mem_desc", "classL4_1_1Kip_1_1Mem__desc.html", "classL4_1_1Kip_1_1Mem__desc" ]
] ],
[ "Type_info", "structL4_1_1Type__info.html", "structL4_1_1Type__info" ],
[ "Kobject_typeid", "structL4_1_1Kobject__typeid.html", "structL4_1_1Kobject__typeid" ],
[ "Kobject_typeid< void >", "structL4_1_1Kobject__typeid_3_01void_01_4.html", null ],
[ "Kobject_t", "classL4_1_1Kobject__t.html", "classL4_1_1Kobject__t" ],
[ "Kobject_2t", "classL4_1_1Kobject__2t.html", "classL4_1_1Kobject__2t" ],
[ "Kobject_3t", "structL4_1_1Kobject__3t.html", "structL4_1_1Kobject__3t" ],
[ "Kobject_demand", "structL4_1_1Kobject__demand.html", null ],
[ "Proto_t", "structL4_1_1Proto__t.html", null ],
[ "Kobject_x", "structL4_1_1Kobject__x.html", null ],
[ "Vm", "classL4_1_1Vm.html", "classL4_1_1Vm" ],
[ "Arm_smccc", "classL4_1_1Arm__smccc.html", "classL4_1_1Arm__smccc" ],
[ "Cap", "classL4_1_1Cap.html", "classL4_1_1Cap" ],
[ "Cap_base", "classL4_1_1Cap__base.html", "classL4_1_1Cap__base" ],
[ "Epiface", "structL4_1_1Epiface.html", "structL4_1_1Epiface" ],
[ "Epiface_t0", "structL4_1_1Epiface__t0.html", "structL4_1_1Epiface__t0" ],
[ "Irqep_t", "structL4_1_1Irqep__t.html", "structL4_1_1Irqep__t" ],
[ "Registry_iface", "classL4_1_1Registry__iface.html", "classL4_1_1Registry__iface" ],
[ "Epiface_t", "structL4_1_1Epiface__t.html", "structL4_1_1Epiface__t" ],
[ "Basic_registry", "classL4_1_1Basic__registry.html", null ],
[ "Server", "classL4_1_1Server.html", "classL4_1_1Server" ],
[ "Debugger", "classL4_1_1Debugger.html", "classL4_1_1Debugger" ],
[ "Exception", "classL4_1_1Exception.html", "classL4_1_1Exception" ],
[ "Factory", "classL4_1_1Factory.html", "classL4_1_1Factory" ],
[ "Iommu", "classL4_1_1Iommu.html", "classL4_1_1Iommu" ],
[ "Ipc_gate", "classL4_1_1Ipc__gate.html", "classL4_1_1Ipc__gate" ],
[ "Irq_eoi", "classL4_1_1Irq__eoi.html", "classL4_1_1Irq__eoi" ],
[ "Triggerable", "structL4_1_1Triggerable.html", "structL4_1_1Triggerable" ],
[ "Irq", "classL4_1_1Irq.html", "classL4_1_1Irq" ],
[ "Icu", "classL4_1_1Icu.html", "classL4_1_1Icu" ],
[ "Kobject", "classL4_1_1Kobject.html", "classL4_1_1Kobject" ],
[ "Meta", "classL4_1_1Meta.html", "classL4_1_1Meta" ],
[ "Io_pager", "classL4_1_1Io__pager.html", "classL4_1_1Io__pager" ],
[ "Pager", "classL4_1_1Pager.html", "classL4_1_1Pager" ],
[ "Platform_control", "classL4_1_1Platform__control.html", "classL4_1_1Platform__control" ],
[ "Rcv_endpoint", "classL4_1_1Rcv__endpoint.html", "classL4_1_1Rcv__endpoint" ],
[ "Scheduler", "classL4_1_1Scheduler.html", "classL4_1_1Scheduler" ],
[ "Semaphore", "structL4_1_1Semaphore.html", "structL4_1_1Semaphore" ],
[ "Smart_cap", "classL4_1_1Smart__cap.html", "classL4_1_1Smart__cap" ],
[ "Task", "classL4_1_1Task.html", "classL4_1_1Task" ],
[ "Thread", "classL4_1_1Thread.html", "classL4_1_1Thread" ],
[ "Thread_group", "classL4_1_1Thread__group.html", "classL4_1_1Thread__group" ],
[ "Vcon", "classL4_1_1Vcon.html", "classL4_1_1Vcon" ],
[ "Poll_timeout_kipclock", "classL4_1_1Poll__timeout__kipclock.html", "classL4_1_1Poll__timeout__kipclock" ],
[ "Alloc_list", "classL4_1_1Alloc__list.html", null ],
[ "IOModifier", "classL4_1_1IOModifier.html", null ],
[ "Exception_tracer", "classL4_1_1Exception__tracer.html", "classL4_1_1Exception__tracer" ],
[ "Base_exception", "classL4_1_1Base__exception.html", "classL4_1_1Base__exception" ],
[ "Runtime_error", "classL4_1_1Runtime__error.html", "classL4_1_1Runtime__error" ],
[ "Out_of_memory", "classL4_1_1Out__of__memory.html", "classL4_1_1Out__of__memory" ],
[ "Element_already_exists", "classL4_1_1Element__already__exists.html", null ],
[ "Unknown_error", "classL4_1_1Unknown__error.html", "classL4_1_1Unknown__error" ],
[ "Element_not_found", "classL4_1_1Element__not__found.html", null ],
[ "Invalid_capability", "classL4_1_1Invalid__capability.html", "classL4_1_1Invalid__capability" ],
[ "Com_error", "classL4_1_1Com__error.html", "classL4_1_1Com__error" ],
[ "Bounds_error", "classL4_1_1Bounds__error.html", null ],
[ "Server_object", "classL4_1_1Server__object.html", "classL4_1_1Server__object" ],
[ "Server_object_t", "structL4_1_1Server__object__t.html", "structL4_1_1Server__object__t" ],
[ "Server_object_x", "structL4_1_1Server__object__x.html", "structL4_1_1Server__object__x" ],
[ "Irq_handler_object", "structL4_1_1Irq__handler__object.html", null ],
[ "Lock_guard", "classL4_1_1Lock__guard.html", "classL4_1_1Lock__guard" ],
[ "String", "classL4_1_1String.html", null ],
[ "Poll_timeout_counter", "classL4_1_1Poll__timeout__counter.html", "classL4_1_1Poll__timeout__counter" ],
[ "Uart_apb", "classL4_1_1Uart__apb.html", "classL4_1_1Uart__apb" ],
[ "Uart", "classL4_1_1Uart.html", "classL4_1_1Uart" ]
] ],
[ "L4drivers", null, [
[ "Mmio_register_block", "structL4drivers_1_1Mmio__register__block.html", null ],
[ "Register_block_base", "structL4drivers_1_1Register__block__base.html", null ],
[ "Register_block_tmpl", "classL4drivers_1_1Register__block__tmpl.html", null ],
[ "Ro_register_tmpl", "classL4drivers_1_1Ro__register__tmpl.html", "classL4drivers_1_1Ro__register__tmpl" ],
[ "Register_tmpl", "classL4drivers_1_1Register__tmpl.html", "classL4drivers_1_1Register__tmpl" ],
[ "Register_block", "classL4drivers_1_1Register__block.html", "classL4drivers_1_1Register__block" ],
[ "Ro_register_block", "classL4drivers_1_1Ro__register__block.html", "classL4drivers_1_1Ro__register__block" ],
[ "Register_block_impl", "structL4drivers_1_1Register__block__impl.html", null ]
] ],
[ "L4Re", "namespaceL4Re.html", [
[ "Ned", null, [
[ "Cmd_control", "classL4Re_1_1Ned_1_1Cmd__control.html", "classL4Re_1_1Ned_1_1Cmd__control" ]
] ],
[ "Vfs", "namespaceL4Re_1_1Vfs.html", [
[ "Be_file", "classL4Re_1_1Vfs_1_1Be__file.html", "classL4Re_1_1Vfs_1_1Be__file" ],
[ "Be_file_system", "classL4Re_1_1Vfs_1_1Be__file__system.html", "classL4Re_1_1Vfs_1_1Be__file__system" ],
[ "Generic_file", "classL4Re_1_1Vfs_1_1Generic__file.html", "classL4Re_1_1Vfs_1_1Generic__file" ],
[ "Directory", "classL4Re_1_1Vfs_1_1Directory.html", "classL4Re_1_1Vfs_1_1Directory" ],
[ "Regular_file", "classL4Re_1_1Vfs_1_1Regular__file.html", "classL4Re_1_1Vfs_1_1Regular__file" ],
[ "Special_file", "classL4Re_1_1Vfs_1_1Special__file.html", "classL4Re_1_1Vfs_1_1Special__file" ],
[ "File", "classL4Re_1_1Vfs_1_1File.html", null ],
[ "Mman", "classL4Re_1_1Vfs_1_1Mman.html", "classL4Re_1_1Vfs_1_1Mman" ],
[ "File_system", "classL4Re_1_1Vfs_1_1File__system.html", "classL4Re_1_1Vfs_1_1File__system" ],
[ "Fs", "classL4Re_1_1Vfs_1_1Fs.html", "classL4Re_1_1Vfs_1_1Fs" ],
[ "Ops", "classL4Re_1_1Vfs_1_1Ops.html", null ]
] ],
[ "Core", null, [
[ "Ref_ptr", "classL4Re_1_1Core_1_1Ref__ptr.html", "classL4Re_1_1Core_1_1Ref__ptr" ]
] ],
[ "Util", "namespaceL4Re_1_1Util.html", [
[ "Names", null, [
[ "Name", "classL4Re_1_1Util_1_1Names_1_1Name.html", null ],
[ "Name_space", "classL4Re_1_1Util_1_1Names_1_1Name__space.html", "classL4Re_1_1Util_1_1Names_1_1Name__space" ]
] ],
[ "Video", null, [
[ "Goos_svr", "classL4Re_1_1Util_1_1Video_1_1Goos__svr.html", "classL4Re_1_1Util_1_1Video_1_1Goos__svr" ]
] ],
[ "Cap_alloc_base", "classL4Re_1_1Util_1_1Cap__alloc__base.html", "classL4Re_1_1Util_1_1Cap__alloc__base" ],
[ "Br_manager", "classL4Re_1_1Util_1_1Br__manager.html", "classL4Re_1_1Util_1_1Br__manager" ],
[ "Br_manager_hooks", "structL4Re_1_1Util_1_1Br__manager__hooks.html", null ],
[ "Br_manager_timeout_hooks", "structL4Re_1_1Util_1_1Br__manager__timeout__hooks.html", null ],
[ "Smart_cap_auto", "classL4Re_1_1Util_1_1Smart__cap__auto.html", null ],
[ "Smart_count_cap", "classL4Re_1_1Util_1_1Smart__count__cap.html", null ],
[ "Ref_cap", "structL4Re_1_1Util_1_1Ref__cap.html", null ],
[ "Ref_del_cap", "structL4Re_1_1Util_1_1Ref__del__cap.html", null ],
[ "_Cap_alloc", "classL4Re_1_1Util_1_1__Cap__alloc.html", "classL4Re_1_1Util_1_1__Cap__alloc" ],
[ "Counter", "structL4Re_1_1Util_1_1Counter.html", "structL4Re_1_1Util_1_1Counter" ],
[ "Counter_atomic", "structL4Re_1_1Util_1_1Counter__atomic.html", "structL4Re_1_1Util_1_1Counter__atomic" ],
[ "Counting_cap_alloc", "classL4Re_1_1Util_1_1Counting__cap__alloc.html", "classL4Re_1_1Util_1_1Counting__cap__alloc" ],
[ "Dataspace_svr", "classL4Re_1_1Util_1_1Dataspace__svr.html", "classL4Re_1_1Util_1_1Dataspace__svr" ],
[ "Event_t", "classL4Re_1_1Util_1_1Event__t.html", "classL4Re_1_1Util_1_1Event__t" ],
[ "Event_buffer_t", "classL4Re_1_1Util_1_1Event__buffer__t.html", "classL4Re_1_1Util_1_1Event__buffer__t" ],
[ "Event_buffer_consumer_t", "classL4Re_1_1Util_1_1Event__buffer__consumer__t.html", "classL4Re_1_1Util_1_1Event__buffer__consumer__t" ],
[ "Event_svr", "classL4Re_1_1Util_1_1Event__svr.html", "classL4Re_1_1Util_1_1Event__svr" ],
[ "Item_alloc_base", "classL4Re_1_1Util_1_1Item__alloc__base.html", null ],
[ "Object_registry", "classL4Re_1_1Util_1_1Object__registry.html", "classL4Re_1_1Util_1_1Object__registry" ],
[ "Registry_server", "classL4Re_1_1Util_1_1Registry__server.html", "classL4Re_1_1Util_1_1Registry__server" ],
[ "Vcon_svr", "classL4Re_1_1Util_1_1Vcon__svr.html", null ],
[ "Bitmap_base", "classL4Re_1_1Util_1_1Bitmap__base.html", "classL4Re_1_1Util_1_1Bitmap__base" ],
[ "Bitmap", "classL4Re_1_1Util_1_1Bitmap.html", "classL4Re_1_1Util_1_1Bitmap" ]
] ],
[ "Video", null, [
[ "Color_component", "classL4Re_1_1Video_1_1Color__component.html", "classL4Re_1_1Video_1_1Color__component" ],
[ "Pixel_info", "classL4Re_1_1Video_1_1Pixel__info.html", "classL4Re_1_1Video_1_1Pixel__info" ],
[ "View", "classL4Re_1_1Video_1_1View.html", "classL4Re_1_1Video_1_1View" ],
[ "Goos", "classL4Re_1_1Video_1_1Goos.html", "classL4Re_1_1Video_1_1Goos" ]
] ],
[ "Cap_alloc", "classL4Re_1_1Cap__alloc.html", "classL4Re_1_1Cap__alloc" ],
[ "Smart_cap_auto", "classL4Re_1_1Smart__cap__auto.html", null ],
[ "Smart_count_cap", "classL4Re_1_1Smart__count__cap.html", "classL4Re_1_1Smart__count__cap" ],
[ "Console", "classL4Re_1_1Console.html", null ],
[ "Dataspace", "classL4Re_1_1Dataspace.html", "classL4Re_1_1Dataspace" ],
[ "Debug_obj", "classL4Re_1_1Debug__obj.html", "classL4Re_1_1Debug__obj" ],
[ "Dma_space", "classL4Re_1_1Dma__space.html", "classL4Re_1_1Dma__space" ],
[ "Env", "classL4Re_1_1Env.html", "classL4Re_1_1Env" ],
[ "Event", "classL4Re_1_1Event.html", "classL4Re_1_1Event" ],
[ "Default_event_payload", "structL4Re_1_1Default__event__payload.html", "structL4Re_1_1Default__event__payload" ],
[ "Event_buffer_t", "classL4Re_1_1Event__buffer__t.html", "classL4Re_1_1Event__buffer__t" ],
[ "Inhibitor", "classL4Re_1_1Inhibitor.html", "classL4Re_1_1Inhibitor" ],
[ "Itas", "classL4Re_1_1Itas.html", "classL4Re_1_1Itas" ],
[ "Log", "classL4Re_1_1Log.html", "classL4Re_1_1Log" ],
[ "Mem_alloc", "classL4Re_1_1Mem__alloc.html", "classL4Re_1_1Mem__alloc" ],
[ "Mmio_space", "structL4Re_1_1Mmio__space.html", "structL4Re_1_1Mmio__space" ],
[ "Namespace", "classL4Re_1_1Namespace.html", "classL4Re_1_1Namespace" ],
[ "Parent", "classL4Re_1_1Parent.html", "classL4Re_1_1Parent" ],
[ "Random", "structL4Re_1_1Random.html", "structL4Re_1_1Random" ],
[ "Rm", "classL4Re_1_1Rm.html", "classL4Re_1_1Rm" ]
] ],
[ "L4vbus", "namespaceL4vbus.html", [
[ "Pm", "classL4vbus_1_1Pm.html", "classL4vbus_1_1Pm" ],
[ "Device", "classL4vbus_1_1Device.html", "classL4vbus_1_1Device" ],
[ "Icu", "classL4vbus_1_1Icu.html", "classL4vbus_1_1Icu" ],
[ "Vbus", "classL4vbus_1_1Vbus.html", "classL4vbus_1_1Vbus" ],
[ "Gpio_pin", "classL4vbus_1_1Gpio__pin.html", "classL4vbus_1_1Gpio__pin" ],
[ "Gpio_module", "classL4vbus_1_1Gpio__module.html", "classL4vbus_1_1Gpio__module" ],
[ "Pci_host_bridge", "classL4vbus_1_1Pci__host__bridge.html", "classL4vbus_1_1Pci__host__bridge" ],
[ "Pci_dev", "classL4vbus_1_1Pci__dev.html", "classL4vbus_1_1Pci__dev" ]
] ],
[ "L4vcpu", null, [
[ "State", "classL4vcpu_1_1State.html", "classL4vcpu_1_1State" ],
[ "Vcpu", "classL4vcpu_1_1Vcpu.html", "classL4vcpu_1_1Vcpu" ]
] ],
[ "L4virtio", "namespaceL4virtio.html", [
[ "Driver", null, [
[ "Device", "classL4virtio_1_1Driver_1_1Device.html", "classL4virtio_1_1Driver_1_1Device" ],
[ "Block_device", "classL4virtio_1_1Driver_1_1Block__device.html", "classL4virtio_1_1Driver_1_1Block__device" ],
[ "Virtio_net_device", "classL4virtio_1_1Driver_1_1Virtio__net__device.html", "classL4virtio_1_1Driver_1_1Virtio__net__device" ],
[ "Virtqueue", "classL4virtio_1_1Driver_1_1Virtqueue.html", "classL4virtio_1_1Driver_1_1Virtqueue" ]
] ],
[ "Svr", null, [
[ "Console", null, [
[ "Features", "structL4virtio_1_1Svr_1_1Console_1_1Features.html", "structL4virtio_1_1Svr_1_1Console_1_1Features" ],
[ "Control_message", "structL4virtio_1_1Svr_1_1Console_1_1Control__message.html", "structL4virtio_1_1Svr_1_1Console_1_1Control__message" ],
[ "Control_request", "structL4virtio_1_1Svr_1_1Console_1_1Control__request.html", "structL4virtio_1_1Svr_1_1Console_1_1Control__request" ],
[ "Port", "structL4virtio_1_1Svr_1_1Console_1_1Port.html", "structL4virtio_1_1Svr_1_1Console_1_1Port" ],
[ "Virtio_con", "classL4virtio_1_1Svr_1_1Console_1_1Virtio__con.html", "classL4virtio_1_1Svr_1_1Console_1_1Virtio__con" ],
[ "Device_port", "structL4virtio_1_1Svr_1_1Console_1_1Device__port.html", "structL4virtio_1_1Svr_1_1Console_1_1Device__port" ],
[ "Device", "classL4virtio_1_1Svr_1_1Console_1_1Device.html", "classL4virtio_1_1Svr_1_1Console_1_1Device" ]
] ],
[ "Scmi", null, [
[ "Scmi_hdr_t", "structL4virtio_1_1Svr_1_1Scmi_1_1Scmi__hdr__t.html", "structL4virtio_1_1Svr_1_1Scmi_1_1Scmi__hdr__t" ],
[ "Base_attr_t", "structL4virtio_1_1Svr_1_1Scmi_1_1Base__attr__t.html", "structL4virtio_1_1Svr_1_1Scmi_1_1Base__attr__t" ],
[ "Performance_attr_t", "structL4virtio_1_1Svr_1_1Scmi_1_1Performance__attr__t.html", "structL4virtio_1_1Svr_1_1Scmi_1_1Performance__attr__t" ],
[ "Performance_domain_attr_t", "structL4virtio_1_1Svr_1_1Scmi_1_1Performance__domain__attr__t.html", "structL4virtio_1_1Svr_1_1Scmi_1_1Performance__domain__attr__t" ],
[ "Performance_describe_levels_n_t", "structL4virtio_1_1Svr_1_1Scmi_1_1Performance__describe__levels__n__t.html", "structL4virtio_1_1Svr_1_1Scmi_1_1Performance__describe__levels__n__t" ],
[ "Performance_describe_level_t", "structL4virtio_1_1Svr_1_1Scmi_1_1Performance__describe__level__t.html", null ],
[ "Proto", "structL4virtio_1_1Svr_1_1Scmi_1_1Proto.html", null ],
[ "Scmi_dev", "classL4virtio_1_1Svr_1_1Scmi_1_1Scmi__dev.html", "classL4virtio_1_1Svr_1_1Scmi_1_1Scmi__dev" ],
[ "Base_proto", "classL4virtio_1_1Svr_1_1Scmi_1_1Base__proto.html", null ],
[ "Perf_proto", "classL4virtio_1_1Svr_1_1Scmi_1_1Perf__proto.html", null ]
] ],
[ "Dev_config", "classL4virtio_1_1Svr_1_1Dev__config.html", "classL4virtio_1_1Svr_1_1Dev__config" ],
[ "Driver_mem_region_t", "classL4virtio_1_1Svr_1_1Driver__mem__region__t.html", "classL4virtio_1_1Svr_1_1Driver__mem__region__t" ],
[ "Driver_mem_list_t", "classL4virtio_1_1Svr_1_1Driver__mem__list__t.html", "classL4virtio_1_1Svr_1_1Driver__mem__list__t" ],
[ "Device_t", "classL4virtio_1_1Svr_1_1Device__t.html", "classL4virtio_1_1Svr_1_1Device__t" ],
[ "Dev_status", "structL4virtio_1_1Svr_1_1Dev__status.html", "structL4virtio_1_1Svr_1_1Dev__status" ],
[ "Dev_features", "structL4virtio_1_1Svr_1_1Dev__features.html", "structL4virtio_1_1Svr_1_1Dev__features" ],
[ "Virtqueue", "classL4virtio_1_1Svr_1_1Virtqueue.html", "classL4virtio_1_1Svr_1_1Virtqueue" ],
[ "Data_buffer", "structL4virtio_1_1Svr_1_1Data__buffer.html", "structL4virtio_1_1Svr_1_1Data__buffer" ],
[ "Bad_descriptor", "structL4virtio_1_1Svr_1_1Bad__descriptor.html", "structL4virtio_1_1Svr_1_1Bad__descriptor" ],
[ "Request_processor", "classL4virtio_1_1Svr_1_1Request__processor.html", "classL4virtio_1_1Svr_1_1Request__processor" ],
[ "Block_dev_base", "classL4virtio_1_1Svr_1_1Block__dev__base.html", "classL4virtio_1_1Svr_1_1Block__dev__base" ],
[ "Block_request", "classL4virtio_1_1Svr_1_1Block__request.html", "classL4virtio_1_1Svr_1_1Block__request" ],
[ "Virtio_gpio", "classL4virtio_1_1Svr_1_1Virtio__gpio.html", "classL4virtio_1_1Svr_1_1Virtio__gpio" ],
[ "Virtio_i2c", "classL4virtio_1_1Svr_1_1Virtio__i2c.html", "classL4virtio_1_1Svr_1_1Virtio__i2c" ],
[ "Virtio_rng", "classL4virtio_1_1Svr_1_1Virtio__rng.html", "classL4virtio_1_1Svr_1_1Virtio__rng" ]
] ],
[ "Device", "classL4virtio_1_1Device.html", "classL4virtio_1_1Device" ],
[ "Ptr", "classL4virtio_1_1Ptr.html", "classL4virtio_1_1Ptr" ],
[ "Virtqueue", "classL4virtio_1_1Virtqueue.html", "classL4virtio_1_1Virtqueue" ]
] ],
[ "Buffer", "structBuffer.html", null ],
[ "Elf32_Auxv", "structElf32__Auxv.html", "structElf32__Auxv" ],
[ "Elf32_Dyn", "structElf32__Dyn.html", "structElf32__Dyn" ],
[ "Elf32_Ehdr", "structElf32__Ehdr.html", "structElf32__Ehdr" ],
[ "Elf32_Phdr", "structElf32__Phdr.html", "structElf32__Phdr" ],
[ "Elf32_Rel", "structElf32__Rel.html", null ],
[ "Elf32_Rela", "structElf32__Rela.html", null ],
[ "Elf32_Shdr", "structElf32__Shdr.html", "structElf32__Shdr" ],
[ "Elf32_Sym", "structElf32__Sym.html", "structElf32__Sym" ],
[ "Elf64_Auxv", "structElf64__Auxv.html", "structElf64__Auxv" ],
[ "Elf64_Dyn", "structElf64__Dyn.html", "structElf64__Dyn" ],
[ "Elf64_Ehdr", "structElf64__Ehdr.html", "structElf64__Ehdr" ],
[ "Elf64_Phdr", "structElf64__Phdr.html", "structElf64__Phdr" ],
[ "Elf64_Rel", "structElf64__Rel.html", null ],
[ "Elf64_Rela", "structElf64__Rela.html", null ],
[ "Elf64_Shdr", "structElf64__Shdr.html", "structElf64__Shdr" ],
[ "Elf64_Sym", "structElf64__Sym.html", "structElf64__Sym" ],
[ "l4_buf_regs_t", "structl4__buf__regs__t.html", "structl4__buf__regs__t" ],
[ "l4_exc_regs_t", "structl4__exc__regs__t.html", "structl4__exc__regs__t" ],
[ "l4_fpage_t", "unionl4__fpage__t.html", "unionl4__fpage__t" ],
[ "l4_icu_info_t", "structl4__icu__info__t.html", "structl4__icu__info__t" ],
[ "l4_icu_msi_info_t", "structl4__icu__msi__info__t.html", "structl4__icu__msi__info__t" ],
[ "l4_kernel_info_mem_desc_t", "structl4__kernel__info__mem__desc__t.html", null ],
[ "l4_kernel_info_t", "structl4__kernel__info__t.html", "structl4__kernel__info__t" ],
[ "l4_msg_regs_t", "unionl4__msg__regs__t.html", "unionl4__msg__regs__t" ],
[ "l4_msgtag_t", "structl4__msgtag__t.html", "structl4__msgtag__t" ],
[ "l4_sched_cpu_set_t", "structl4__sched__cpu__set__t.html", "structl4__sched__cpu__set__t" ],
[ "l4_sched_param_t", "structl4__sched__param__t.html", "structl4__sched__param__t" ],
[ "l4_snd_fpage_t", "structl4__snd__fpage__t.html", "structl4__snd__fpage__t" ],
[ "l4_thread_regs_t", "structl4__thread__regs__t.html", "structl4__thread__regs__t" ],
[ "l4_timeout_s", "structl4__timeout__s.html", "structl4__timeout__s" ],
[ "l4_timeout_t", "unionl4__timeout__t.html", "unionl4__timeout__t" ],
[ "l4_vcon_attr_t", "structl4__vcon__attr__t.html", "structl4__vcon__attr__t" ],
[ "l4_vcpu_arch_state_t", "structl4__vcpu__arch__state__t.html", null ],
[ "l4_vcpu_ipc_regs_t", "structl4__vcpu__ipc__regs__t.html", null ],
[ "l4_vcpu_regs_t", "structl4__vcpu__regs__t.html", "structl4__vcpu__regs__t" ],
[ "l4_vcpu_state_t", "structl4__vcpu__state__t.html", "structl4__vcpu__state__t" ],
[ "l4_vm_svm_vmcb_control_area", "structl4__vm__svm__vmcb__control__area.html", null ],
[ "l4_vm_svm_vmcb_state_save_area", "structl4__vm__svm__vmcb__state__save__area.html", null ],
[ "l4_vm_svm_vmcb_state_save_area_seg", "structl4__vm__svm__vmcb__state__save__area__seg.html", null ],
[ "l4_vm_svm_vmcb_t", "structl4__vm__svm__vmcb__t.html", null ],
[ "l4_vm_tz_state", "structl4__vm__tz__state.html", null ],
[ "l4_vm_vmx_vcpu_infos_t", "structl4__vm__vmx__vcpu__infos__t.html", "structl4__vm__vmx__vcpu__infos__t" ],
[ "l4_vm_vmx_vcpu_state_t", "structl4__vm__vmx__vcpu__state__t.html", null ],
[ "l4_vm_vmx_vcpu_vmcs_t", "structl4__vm__vmx__vcpu__vmcs__t.html", null ],
[ "l4_vmx_offset_table_t", "structl4__vmx__offset__table__t.html", null ],
[ "l4re_aux_t", "structl4re__aux__t.html", "structl4re__aux__t" ],
[ "l4re_ds_stats_t", "structl4re__ds__stats__t.html", "structl4re__ds__stats__t" ],
[ "l4re_elf_aux_mword_t", "structl4re__elf__aux__mword__t.html", null ],
[ "l4re_elf_aux_t", "structl4re__elf__aux__t.html", null ],
[ "l4re_elf_aux_vma_t", "structl4re__elf__aux__vma__t.html", null ],
[ "l4re_env_cap_entry_t", "structl4re__env__cap__entry__t.html", "structl4re__env__cap__entry__t" ],
[ "l4re_env_t", "structl4re__env__t.html", "structl4re__env__t" ],
[ "l4re_event_t", "structl4re__event__t.html", "structl4re__event__t" ],
[ "l4re_video_color_component_t", "structl4re__video__color__component__t.html", "structl4re__video__color__component__t" ],
[ "l4re_video_goos_info_t", "structl4re__video__goos__info__t.html", "structl4re__video__goos__info__t" ],
[ "l4re_video_pixel_info_t", "structl4re__video__pixel__info__t.html", "structl4re__video__pixel__info__t" ],
[ "l4re_video_view_info_t", "structl4re__video__view__info__t.html", "structl4re__video__view__info__t" ],
[ "l4re_video_view_t", "structl4re__video__view__t.html", null ],
[ "l4shmc_ringbuf_head_t", "structl4shmc__ringbuf__head__t.html", "structl4shmc__ringbuf__head__t" ],
[ "l4shmc_ringbuf_t", "structl4shmc__ringbuf__t.html", "structl4shmc__ringbuf__t" ],
[ "l4util_l4mod_info", "structl4util__l4mod__info.html", "structl4util__l4mod__info" ],
[ "l4util_l4mod_mod", "structl4util__l4mod__mod.html", "structl4util__l4mod__mod" ],
[ "l4util_mb_addr_range_t", "structl4util__mb__addr__range__t.html", "structl4util__mb__addr__range__t" ],
[ "l4util_mb_apm_t", "structl4util__mb__apm__t.html", null ],
[ "l4util_mb_drive_t", "structl4util__mb__drive__t.html", "structl4util__mb__drive__t" ],
[ "l4util_mb_info_t", "structl4util__mb__info__t.html", "structl4util__mb__info__t" ],
[ "l4util_mb_mod_t", "structl4util__mb__mod__t.html", "structl4util__mb__mod__t" ],
[ "l4util_mb_vbe_ctrl_t", "structl4util__mb__vbe__ctrl__t.html", null ],
[ "l4util_mb_vbe_mode_t", "structl4util__mb__vbe__mode__t.html", "structl4util__mb__vbe__mode__t" ],
[ "l4vbus_device_t", "structl4vbus__device__t.html", "structl4vbus__device__t" ],
[ "l4vbus_resource_t", "structl4vbus__resource__t.html", "structl4vbus__resource__t" ],
[ "l4virtio_block_config_t", "structl4virtio__block__config__t.html", "structl4virtio__block__config__t" ],
[ "l4virtio_block_discard_t", "structl4virtio__block__discard__t.html", null ],
[ "l4virtio_block_header_t", "structl4virtio__block__header__t.html", "structl4virtio__block__header__t" ],
[ "l4virtio_config_hdr_t", "structl4virtio__config__hdr__t.html", "structl4virtio__config__hdr__t" ],
[ "l4virtio_config_queue_t", "structl4virtio__config__queue__t.html", "structl4virtio__config__queue__t" ],
[ "l4virtio_input_absinfo_t", "structl4virtio__input__absinfo__t.html", null ],
[ "l4virtio_input_config_t", "structl4virtio__input__config__t.html", null ],
[ "l4virtio_input_devids_t", "structl4virtio__input__devids__t.html", null ],
[ "l4virtio_input_event_t", "structl4virtio__input__event__t.html", null ],
[ "l4virtio_net_config_t", "structl4virtio__net__config__t.html", null ],
[ "l4virtio_net_header_t", "structl4virtio__net__header__t.html", null ],
[ "L4virtio_port", "classL4virtio__port.html", "classL4virtio__port" ],
[ "Mac_addr", "classMac__addr.html", "classMac__addr" ],
[ "Mac_table", "classMac__table.html", "classMac__table" ],
[ "Net_transfer", "classNet__transfer.html", "classNet__transfer" ],
[ "Rm", "classRm.html", "classRm" ],
[ "Switch_factory", "classSwitch__factory.html", "classSwitch__factory" ],
[ "Virtio_net", "classVirtio__net.html", "classVirtio__net" ],
[ "Virtio_net_request", "classVirtio__net__request.html", "classVirtio__net__request" ],
[ "Virtio_switch", "classVirtio__switch.html", "classVirtio__switch" ],
[ "Virtio_vlan_mangle", "classVirtio__vlan__mangle.html", "classVirtio__vlan__mangle" ]
];