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Viktor Reusch
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<div class="headertitle"><div class="title">vCPU API <div class="ingroups"><a class="el" href="group__l4__api.html">Base API</a> &raquo; <a class="el" href="group__l4__kernel__object__api.html">Kernel Objects</a> &raquo; <a class="el" href="group__l4__thread__api.html">Thread</a></div></div></div>
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<p>vCPU API.
<a href="#details">More...</a></p>
<div id="dynsection-0" onclick="return dynsection.toggleVisibility(this)" class="dynheader closed" style="cursor:pointer;"><span class="dynarrow"><span class="arrowhead closed"></span></span>Collaboration diagram for vCPU API:</div>
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<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-nested-classes" class="groupheader"><a id="nested-classes" name="nested-classes"></a>
Data Structures</h2></td></tr>
<tr class="memitem:l4_5Fvcpu_5Fstate_5Ft" id="r_l4_5Fvcpu_5Fstate_5Ft"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structl4__vcpu__state__t.html">l4_vcpu_state_t</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">State of a vCPU. <a href="structl4__vcpu__state__t.html#details">More...</a><br /></td></tr>
<tr class="memitem:l4_5Fvcpu_5Fregs_5Ft" id="r_l4_5Fvcpu_5Fregs_5Ft"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structl4__vcpu__regs__t.html">l4_vcpu_regs_t</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">vCPU registers. <a href="structl4__vcpu__regs__t.html#details">More...</a><br /></td></tr>
<tr class="memitem:l4_5Fvcpu_5Fipc_5Fregs_5Ft" id="r_l4_5Fvcpu_5Fipc_5Fregs_5Ft"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structl4__vcpu__ipc__regs__t.html">l4_vcpu_ipc_regs_t</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">vCPU message registers. <a href="structl4__vcpu__ipc__regs__t.html#details">More...</a><br /></td></tr>
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Typedefs</h2></td></tr>
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<tr class="memdesc:ga947902acd03617c67200def55c29a62b"><td class="mdescLeft">&#160;</td><td class="mdescRight">State of a vCPU. <br /></td></tr>
<tr class="memitem:gab6bd3b349dcc885ad4ebee3379966cc0" id="r_gab6bd3b349dcc885ad4ebee3379966cc0"><td class="memItemLeft" align="right" valign="top"><a id="gab6bd3b349dcc885ad4ebee3379966cc0" name="gab6bd3b349dcc885ad4ebee3379966cc0"></a>
typedef struct l4_vcpu_regs_t&#160;</td><td class="memItemRight" valign="bottom"><b>l4_vcpu_regs_t</b></td></tr>
<tr class="memdesc:gab6bd3b349dcc885ad4ebee3379966cc0"><td class="mdescLeft">&#160;</td><td class="mdescRight">vCPU registers. <br /></td></tr>
<tr class="memitem:ga8655f00476dd34b9030b89ec01da8fd1" id="r_ga8655f00476dd34b9030b89ec01da8fd1"><td class="memItemLeft" align="right" valign="top"><a id="ga8655f00476dd34b9030b89ec01da8fd1" name="ga8655f00476dd34b9030b89ec01da8fd1"></a>
typedef struct l4_vcpu_ipc_regs_t&#160;</td><td class="memItemRight" valign="bottom"><b>l4_vcpu_ipc_regs_t</b></td></tr>
<tr class="memdesc:ga8655f00476dd34b9030b89ec01da8fd1"><td class="mdescLeft">&#160;</td><td class="mdescRight">vCPU message registers. <br /></td></tr>
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typedef <a class="el" href="structl4__exc__regs__t.html">l4_exc_regs_t</a>&#160;</td><td class="memItemRight" valign="bottom"><b>l4_vcpu_regs_t</b></td></tr>
<tr class="memdesc:ga9ebfcab2932e7f9558c6d4f2e41060fc"><td class="mdescLeft">&#160;</td><td class="mdescRight">vCPU registers. <br /></td></tr>
<tr class="memitem:ga8655f00476dd34b9030b89ec01da8fd1" id="r_ga8655f00476dd34b9030b89ec01da8fd1"><td class="memItemLeft" align="right" valign="top"><a id="ga8655f00476dd34b9030b89ec01da8fd1" name="ga8655f00476dd34b9030b89ec01da8fd1"></a>
typedef struct l4_vcpu_ipc_regs_t&#160;</td><td class="memItemRight" valign="bottom"><b>l4_vcpu_ipc_regs_t</b></td></tr>
<tr class="memdesc:ga8655f00476dd34b9030b89ec01da8fd1"><td class="mdescLeft">&#160;</td><td class="mdescRight">vCPU message registers. <br /></td></tr>
<tr class="memitem:gab6bd3b349dcc885ad4ebee3379966cc0" id="r_gab6bd3b349dcc885ad4ebee3379966cc0"><td class="memItemLeft" align="right" valign="top"><a id="gab6bd3b349dcc885ad4ebee3379966cc0" name="gab6bd3b349dcc885ad4ebee3379966cc0"></a>
typedef struct l4_vcpu_regs_t&#160;</td><td class="memItemRight" valign="bottom"><b>l4_vcpu_regs_t</b></td></tr>
<tr class="memdesc:gab6bd3b349dcc885ad4ebee3379966cc0"><td class="mdescLeft">&#160;</td><td class="mdescRight">vCPU registers. <br /></td></tr>
<tr class="memitem:ga8655f00476dd34b9030b89ec01da8fd1" id="r_ga8655f00476dd34b9030b89ec01da8fd1"><td class="memItemLeft" align="right" valign="top"><a id="ga8655f00476dd34b9030b89ec01da8fd1" name="ga8655f00476dd34b9030b89ec01da8fd1"></a>
typedef struct l4_vcpu_ipc_regs_t&#160;</td><td class="memItemRight" valign="bottom"><b>l4_vcpu_ipc_regs_t</b></td></tr>
<tr class="memdesc:ga8655f00476dd34b9030b89ec01da8fd1"><td class="mdescLeft">&#160;</td><td class="mdescRight">vCPU message registers. <br /></td></tr>
<tr class="memitem:gab6bd3b349dcc885ad4ebee3379966cc0" id="r_gab6bd3b349dcc885ad4ebee3379966cc0"><td class="memItemLeft" align="right" valign="top"><a id="gab6bd3b349dcc885ad4ebee3379966cc0" name="gab6bd3b349dcc885ad4ebee3379966cc0"></a>
typedef struct l4_vcpu_regs_t&#160;</td><td class="memItemRight" valign="bottom"><b>l4_vcpu_regs_t</b></td></tr>
<tr class="memdesc:gab6bd3b349dcc885ad4ebee3379966cc0"><td class="mdescLeft">&#160;</td><td class="mdescRight">vCPU registers. <br /></td></tr>
<tr class="memitem:ga8655f00476dd34b9030b89ec01da8fd1" id="r_ga8655f00476dd34b9030b89ec01da8fd1"><td class="memItemLeft" align="right" valign="top"><a id="ga8655f00476dd34b9030b89ec01da8fd1" name="ga8655f00476dd34b9030b89ec01da8fd1"></a>
typedef struct l4_vcpu_ipc_regs_t&#160;</td><td class="memItemRight" valign="bottom"><b>l4_vcpu_ipc_regs_t</b></td></tr>
<tr class="memdesc:ga8655f00476dd34b9030b89ec01da8fd1"><td class="mdescLeft">&#160;</td><td class="mdescRight">vCPU message registers. <br /></td></tr>
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<tr class="heading"><td colspan="2"><h2 id="header-enum-members" class="groupheader"><a id="enum-members" name="enum-members"></a>
Enumerations</h2></td></tr>
<tr class="memitem:ga648aa99b07fd60d941c5ebb25f746967" id="r_ga648aa99b07fd60d941c5ebb25f746967"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga648aa99b07fd60d941c5ebb25f746967">L4_vcpu_state_flags</a> { <br />
&#160;&#160;<a class="el" href="#gga648aa99b07fd60d941c5ebb25f746967a6283b6f4dc69ad65e5ab99f0c35044a9">L4_VCPU_F_IRQ</a> = 0x01
, <a class="el" href="#gga648aa99b07fd60d941c5ebb25f746967ae6673be1a1c99c57418bb5bfc5ae627a">L4_VCPU_F_PAGE_FAULTS</a> = 0x02
, <a class="el" href="#gga648aa99b07fd60d941c5ebb25f746967a1dcf416d1db40300001e57ab981a7107">L4_VCPU_F_EXCEPTIONS</a> = 0x04
, <a class="el" href="#gga648aa99b07fd60d941c5ebb25f746967a14d8e402739cff88ebf7e2810f306c4b">L4_VCPU_F_USER_MODE</a> = 0x20
, <br />
&#160;&#160;<a class="el" href="#gga648aa99b07fd60d941c5ebb25f746967a82a729a14e0b6a85b3f0ce35803f12ed">L4_VCPU_F_FPU_ENABLED</a> = 0x80
<br />
}</td></tr>
<tr class="memdesc:ga648aa99b07fd60d941c5ebb25f746967"><td class="mdescLeft">&#160;</td><td class="mdescRight">State flags of a vCPU. <a href="#ga648aa99b07fd60d941c5ebb25f746967">More...</a><br /></td></tr>
<tr class="memitem:ga4a26ee99aaf5f75087c6918f57c3d4d5" id="r_ga4a26ee99aaf5f75087c6918f57c3d4d5"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga4a26ee99aaf5f75087c6918f57c3d4d5">L4_vcpu_sticky_flags</a> { <a class="el" href="#gga4a26ee99aaf5f75087c6918f57c3d4d5afdc98b96983362771316581981ded160">L4_VCPU_SF_IRQ_PENDING</a> = 0x01
}</td></tr>
<tr class="memdesc:ga4a26ee99aaf5f75087c6918f57c3d4d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sticky flags of a vCPU. <a href="#ga4a26ee99aaf5f75087c6918f57c3d4d5">More...</a><br /></td></tr>
<tr class="memitem:gaa9c9426f606dfa123ace57a1081e4e1b" id="r_gaa9c9426f606dfa123ace57a1081e4e1b"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaa9c9426f606dfa123ace57a1081e4e1b">L4_vcpu_state_offset</a> { <a class="el" href="#ggaa9c9426f606dfa123ace57a1081e4e1ba970100e3dd8000f263688f50d6fcbda3">L4_VCPU_OFFSET_EXT_STATE</a> = 0x180
, <a class="el" href="#ggaa9c9426f606dfa123ace57a1081e4e1ba51d123b064652c03ed78714ec92615e5">L4_VCPU_OFFSET_EXT_INFOS</a> = 0x100
}</td></tr>
<tr class="memdesc:gaa9c9426f606dfa123ace57a1081e4e1b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offsets for vCPU state layouts. <a href="#gaa9c9426f606dfa123ace57a1081e4e1b">More...</a><br /></td></tr>
<tr class="memitem:gaa9c9426f606dfa123ace57a1081e4e1b" id="r_gaa9c9426f606dfa123ace57a1081e4e1b"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaa9c9426f606dfa123ace57a1081e4e1b">L4_vcpu_state_offset</a> { <a class="el" href="#ggaa9c9426f606dfa123ace57a1081e4e1ba970100e3dd8000f263688f50d6fcbda3">L4_VCPU_OFFSET_EXT_STATE</a> = 0x280
, <a class="el" href="#ggaa9c9426f606dfa123ace57a1081e4e1ba51d123b064652c03ed78714ec92615e5">L4_VCPU_OFFSET_EXT_INFOS</a> = 0x200
}</td></tr>
<tr class="memdesc:gaa9c9426f606dfa123ace57a1081e4e1b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offsets for vCPU state layouts. <a href="#gaa9c9426f606dfa123ace57a1081e4e1b">More...</a><br /></td></tr>
<tr class="memitem:gaa9c9426f606dfa123ace57a1081e4e1b" id="r_gaa9c9426f606dfa123ace57a1081e4e1b"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaa9c9426f606dfa123ace57a1081e4e1b">L4_vcpu_state_offset</a> { <a class="el" href="#ggaa9c9426f606dfa123ace57a1081e4e1ba970100e3dd8000f263688f50d6fcbda3">L4_VCPU_OFFSET_EXT_STATE</a> = 0x400
, <a class="el" href="#ggaa9c9426f606dfa123ace57a1081e4e1ba51d123b064652c03ed78714ec92615e5">L4_VCPU_OFFSET_EXT_INFOS</a> = 0x200
}</td></tr>
<tr class="memdesc:gaa9c9426f606dfa123ace57a1081e4e1b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offsets for vCPU state layouts. <a href="#gaa9c9426f606dfa123ace57a1081e4e1b">More...</a><br /></td></tr>
<tr class="memitem:gaa9c9426f606dfa123ace57a1081e4e1b" id="r_gaa9c9426f606dfa123ace57a1081e4e1b"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaa9c9426f606dfa123ace57a1081e4e1b">L4_vcpu_state_offset</a> { <a class="el" href="#ggaa9c9426f606dfa123ace57a1081e4e1ba970100e3dd8000f263688f50d6fcbda3">L4_VCPU_OFFSET_EXT_STATE</a> = 0x400
, <a class="el" href="#ggaa9c9426f606dfa123ace57a1081e4e1ba51d123b064652c03ed78714ec92615e5">L4_VCPU_OFFSET_EXT_INFOS</a> = 0x200
}</td></tr>
<tr class="memdesc:gaa9c9426f606dfa123ace57a1081e4e1b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offsets for vCPU state layouts. <a href="#gaa9c9426f606dfa123ace57a1081e4e1b">More...</a><br /></td></tr>
</table>
<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<p>vCPU API. </p>
<p>The vCPU API in <a class="el" href="namespaceL4Re.html" title="L4Re C++ Interfaces.">L4Re</a> implements virtual processors (vCPUs) on top of <a class="el" href="classL4_1_1Thread.html" title="C++ L4 kernel thread interface, see Thread for the C interface.">L4::Thread</a>. This API can be used for user level threading, operating system rehosting (see L4Linux) and virtualization.</p>
<p>You switch a thread into <span class="tt">vCPU</span> operation with <a class="el" href="classL4_1_1Thread.html#a94a6d8a5a7a78fa99ef3c6358e0a0459" title="Enable the vCPU feature for the thread.">L4::Thread::vcpu_control</a>.</p>
<p>In vCPU mode, incoming IPC can be redirected to a handler function. If an IPC is sent to the vCPU, the thread's normal execution is interrupted and the handler called. Which kind of IPC is redirected is specified by the <a class="el" href="#ga648aa99b07fd60d941c5ebb25f746967" title="State flags of a vCPU.">L4_vcpu_state_flags</a> set in the <a class="el" href="structl4__vcpu__state__t.html#a70f0d1784cad3401b5e6df1876b33892" title="Current vCPU state. See L4_vcpu_state_flags.">l4_vcpu_state_t::state</a> field of <span class="tt">vcpu_state</span>. All events enabled in the <span class="tt">vcpu_state</span> field are redirected to the handler. The handler is set via <a class="el" href="structl4__vcpu__state__t.html#ad38f88918b67a3e83aff1218ab7a9de0" title="IP for entry.">l4_vcpu_state_t::entry_ip</a> and <a class="el" href="structl4__vcpu__state__t.html#a1f45174954aa47bb2f21b7b90bed250e" title="Stack pointer for entry (when coming from user task).">l4_vcpu_state_t::entry_sp</a>. IPC redirection works independent of "kernel" and "user" mode, but see <a class="el" href="structl4__vcpu__state__t.html#a1f45174954aa47bb2f21b7b90bed250e" title="Stack pointer for entry (when coming from user task).">l4_vcpu_state_t::entry_sp</a>. When the entry handler is called, the UTCB contains the result of the IPC and content normally found in CPU register is in <a class="el" href="structl4__vcpu__state__t.html#ae8656b7619f0fc74026455b2a260e39e" title="IPC state.">l4_vcpu_state_t::i</a>.</p>
<p>Furthermore, the thread can execute in the context of different tasks, called the "kernel" and the "user" mode. The kernel task is the one to which the thread was originally bound via <a class="el" href="classL4_1_1Thread.html#a4252cd0ad4bdfa00cdc61b5fd2317aef" title="Commit the given thread-attributes object.">L4::Thread::control()</a>. Execution starts in the kernel task and it is always switched to when the asynchronous IPC handler is invoked. When returning from the handler via <a class="el" href="group__l4__thread__api.html#ga6e0620f6b1119d84eac90adad52eabf8" title="vCPU return from event handler.">l4_thread_vcpu_resume_start()</a> and <a class="el" href="group__l4__thread__api.html#gaaf8bb1c28a014326dd381bc2d3478da8" title="Commit vCPU resume.">l4_thread_vcpu_resume_commit()</a>, a different user task can be specified by setting <a class="el" href="structl4__vcpu__state__t.html#ade963d62e21e225390c94f8e24a6bec1" title="User task to use.">l4_vcpu_state_t::user_task</a> and enabling the <a class="el" href="#gga648aa99b07fd60d941c5ebb25f746967a14d8e402739cff88ebf7e2810f306c4b" title="User task will be used.">L4_VCPU_F_USER_MODE</a> flag in <a class="el" href="structl4__vcpu__state__t.html#a70f0d1784cad3401b5e6df1876b33892" title="Current vCPU state. See L4_vcpu_state_flags.">l4_vcpu_state_t::state</a>. Note that the kernel may cache the user task internally, see <a class="el" href="group__l4__thread__api.html#gaaf8bb1c28a014326dd381bc2d3478da8" title="Commit vCPU resume.">l4_thread_vcpu_resume_commit()</a>.</p>
<p>If the <a class="el" href="#gga648aa99b07fd60d941c5ebb25f746967a14d8e402739cff88ebf7e2810f306c4b" title="User task will be used.">L4_VCPU_F_USER_MODE</a> flag is enabled, the following flags will be automatically enabled in <a class="el" href="structl4__vcpu__state__t.html#a70f0d1784cad3401b5e6df1876b33892" title="Current vCPU state. See L4_vcpu_state_flags.">l4_vcpu_state_t::state</a> on <a class="el" href="classL4_1_1Thread.html#a72ce9179f1b083a65f0d4caa5b6aee67" title="Resume from vCPU asynchronous IPC handler, commit.">L4::Thread::vcpu_resume_commit()</a>:</p><ul>
<li><a class="el" href="#gga648aa99b07fd60d941c5ebb25f746967a6283b6f4dc69ad65e5ab99f0c35044a9" title="Receiving of IRQs and IPC enabled.">L4_VCPU_F_IRQ</a></li>
<li><a class="el" href="#gga648aa99b07fd60d941c5ebb25f746967ae6673be1a1c99c57418bb5bfc5ae627a" title="Page faults enabled.">L4_VCPU_F_PAGE_FAULTS</a></li>
<li><a class="el" href="#gga648aa99b07fd60d941c5ebb25f746967a1dcf416d1db40300001e57ab981a7107" title="Exceptions enabled.">L4_VCPU_F_EXCEPTIONS</a></li>
</ul>
<p>When the kernel mode is entered, the following flags will be automatically disabled in <a class="el" href="structl4__vcpu__state__t.html#a70f0d1784cad3401b5e6df1876b33892" title="Current vCPU state. See L4_vcpu_state_flags.">l4_vcpu_state_t::state</a>:</p><ul>
<li><a class="el" href="#gga648aa99b07fd60d941c5ebb25f746967a6283b6f4dc69ad65e5ab99f0c35044a9" title="Receiving of IRQs and IPC enabled.">L4_VCPU_F_IRQ</a></li>
<li><a class="el" href="#gga648aa99b07fd60d941c5ebb25f746967ae6673be1a1c99c57418bb5bfc5ae627a" title="Page faults enabled.">L4_VCPU_F_PAGE_FAULTS</a></li>
<li><a class="el" href="#gga648aa99b07fd60d941c5ebb25f746967a14d8e402739cff88ebf7e2810f306c4b" title="User task will be used.">L4_VCPU_F_USER_MODE</a></li>
</ul>
<p>Extended vCPU operation is used for hardware CPU virtualization. It can be enabled with <a class="el" href="classL4_1_1Thread.html#ac341b827b00c21bc3753c30163e0f173" title="Enable the extended vCPU feature for the thread.">L4::Thread::vcpu_control_ext()</a>.</p>
<p><a class="el" href="group__api__libvcpu.html">vCPU Support Library</a> defines a convenience API for working with vCPUs.</p>
<dl class="section see"><dt>See also</dt><dd><a class="el" href="group__api__libvcpu.html" title="vCPU handling functionality.">vCPU Support Library</a> </dd></dl>
<a name="doc-enum-members" id="doc-enum-members"></a><h2 id="header-doc-enum-members" class="groupheader">Enumeration Type Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#ga648aa99b07fd60d941c5ebb25f746967">&#9670;&#160;</a></span>L4_vcpu_state_flags</h2>
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<td class="memname">enum <a class="el" href="#ga648aa99b07fd60d941c5ebb25f746967">L4_vcpu_state_flags</a></td>
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<p>State flags of a vCPU. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga648aa99b07fd60d941c5ebb25f746967a6283b6f4dc69ad65e5ab99f0c35044a9" name="gga648aa99b07fd60d941c5ebb25f746967a6283b6f4dc69ad65e5ab99f0c35044a9"></a>L4_VCPU_F_IRQ&#160;</td><td class="fielddoc"><p>Receiving of IRQs and IPC enabled. </p>
<p>While this flag is not set, the corresponding vCPU thread will not receive any IPC and threads attempting to send an IPC to this thread will block (according to the selected send timeout).</p>
<dl class="section note"><dt>Note</dt><dd>On <a class="el" href="classL4_1_1Thread.html#a72ce9179f1b083a65f0d4caa5b6aee67" title="Resume from vCPU asynchronous IPC handler, commit.">L4::Thread::vcpu_resume_commit()</a> this flag is automatically enabled in <a class="el" href="structl4__vcpu__state__t.html#a70f0d1784cad3401b5e6df1876b33892" title="Current vCPU state. See L4_vcpu_state_flags.">l4_vcpu_state_t::state</a> if <a class="el" href="#gga648aa99b07fd60d941c5ebb25f746967a14d8e402739cff88ebf7e2810f306c4b" title="User task will be used.">L4_VCPU_F_USER_MODE</a> is enabled. </dd>
<dd>
When the kernel mode is entered, this flags is automatically disabled in <a class="el" href="structl4__vcpu__state__t.html#a70f0d1784cad3401b5e6df1876b33892" title="Current vCPU state. See L4_vcpu_state_flags.">l4_vcpu_state_t::state</a>. </dd></dl>
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<tr><td class="fieldname"><a id="gga648aa99b07fd60d941c5ebb25f746967ae6673be1a1c99c57418bb5bfc5ae627a" name="gga648aa99b07fd60d941c5ebb25f746967ae6673be1a1c99c57418bb5bfc5ae627a"></a>L4_VCPU_F_PAGE_FAULTS&#160;</td><td class="fielddoc"><p>Page faults enabled. </p>
<p>If this flag is set, a page fault switches to kernel mode (potentially causing a VM exit) and calls the entry handler. If this flag is not set, a page fault generates a page fault IPC to the pager of the vCPU thread.</p>
<dl class="section note"><dt>Note</dt><dd>IPC redirection for page faults controlled by this flag works independent of "kernel" and "user" mode. </dd>
<dd>
On <a class="el" href="classL4_1_1Thread.html#a72ce9179f1b083a65f0d4caa5b6aee67" title="Resume from vCPU asynchronous IPC handler, commit.">L4::Thread::vcpu_resume_commit()</a> this flag is automatically enabled in <a class="el" href="structl4__vcpu__state__t.html#a70f0d1784cad3401b5e6df1876b33892" title="Current vCPU state. See L4_vcpu_state_flags.">l4_vcpu_state_t::state</a> if <a class="el" href="#gga648aa99b07fd60d941c5ebb25f746967a14d8e402739cff88ebf7e2810f306c4b" title="User task will be used.">L4_VCPU_F_USER_MODE</a> is enabled. </dd>
<dd>
When the kernel mode is entered, this flags is automatically disabled in <a class="el" href="structl4__vcpu__state__t.html#a70f0d1784cad3401b5e6df1876b33892" title="Current vCPU state. See L4_vcpu_state_flags.">l4_vcpu_state_t::state</a>. </dd></dl>
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<tr><td class="fieldname"><a id="gga648aa99b07fd60d941c5ebb25f746967a1dcf416d1db40300001e57ab981a7107" name="gga648aa99b07fd60d941c5ebb25f746967a1dcf416d1db40300001e57ab981a7107"></a>L4_VCPU_F_EXCEPTIONS&#160;</td><td class="fielddoc"><p>Exceptions enabled. </p>
<p>If this flag is set, then, on the event of an exception, the vCPU switches to kernel mode (potentially causing a VM exit) and calls the entry handler. If this flag is not set, an exception generates an exception IPC to the exception handler of the vCPU thread.</p>
<dl class="section note"><dt>Note</dt><dd>IPC redirection for exceptions controlled by this flag works independent of "kernel" and "user" mode. </dd>
<dd>
On <a class="el" href="classL4_1_1Thread.html#a72ce9179f1b083a65f0d4caa5b6aee67" title="Resume from vCPU asynchronous IPC handler, commit.">L4::Thread::vcpu_resume_commit()</a> this flag is automatically enabled in <a class="el" href="structl4__vcpu__state__t.html#a70f0d1784cad3401b5e6df1876b33892" title="Current vCPU state. See L4_vcpu_state_flags.">l4_vcpu_state_t::state</a> if <a class="el" href="#gga648aa99b07fd60d941c5ebb25f746967a14d8e402739cff88ebf7e2810f306c4b" title="User task will be used.">L4_VCPU_F_USER_MODE</a> is enabled. </dd></dl>
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<tr><td class="fieldname"><a id="gga648aa99b07fd60d941c5ebb25f746967a14d8e402739cff88ebf7e2810f306c4b" name="gga648aa99b07fd60d941c5ebb25f746967a14d8e402739cff88ebf7e2810f306c4b"></a>L4_VCPU_F_USER_MODE&#160;</td><td class="fielddoc"><p>User task will be used. </p>
<p>If set, the vCPU switches to user mode on next <a class="el" href="classL4_1_1Thread.html#a72ce9179f1b083a65f0d4caa5b6aee67" title="Resume from vCPU asynchronous IPC handler, commit.">L4::Thread::vcpu_resume_commit()</a>. If clear, the vCPU stays in "kernel" mode.</p>
<dl class="section note"><dt>Note</dt><dd>When the kernel mode is entered, this flags is automatically disabled in <a class="el" href="structl4__vcpu__state__t.html#a70f0d1784cad3401b5e6df1876b33892" title="Current vCPU state. See L4_vcpu_state_flags.">l4_vcpu_state_t::state</a>. </dd></dl>
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<tr><td class="fieldname"><a id="gga648aa99b07fd60d941c5ebb25f746967a82a729a14e0b6a85b3f0ce35803f12ed" name="gga648aa99b07fd60d941c5ebb25f746967a82a729a14e0b6a85b3f0ce35803f12ed"></a>L4_VCPU_F_FPU_ENABLED&#160;</td><td class="fielddoc"><p>FPU enabled. </p>
<p>This flag is only relevant if <a class="el" href="#gga648aa99b07fd60d941c5ebb25f746967a14d8e402739cff88ebf7e2810f306c4b" title="User task will be used.">L4_VCPU_F_USER_MODE</a> is set. Setting this flag allows code in vCPU mode to use the FPU. IF this flag is not set, any FPU operation will trigger a corresponding exception (FPU fault). </p>
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<p class="definition">Definition at line <a class="el" href="sys_2vcpu_8h_source.html#l00101">101</a> of file <a class="el" href="sys_2vcpu_8h_source.html">vcpu.h</a>.</p>
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<h2 class="memtitle"><span class="permalink"><a href="#gaa9c9426f606dfa123ace57a1081e4e1b">&#9670;&#160;</a></span>L4_vcpu_state_offset <span class="overload">[1/4]</span></h2>
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<td class="memname">enum <a class="el" href="#gaa9c9426f606dfa123ace57a1081e4e1b">L4_vcpu_state_offset</a></td>
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<p>Offsets for vCPU state layouts. </p>
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ggaa9c9426f606dfa123ace57a1081e4e1ba970100e3dd8000f263688f50d6fcbda3" name="ggaa9c9426f606dfa123ace57a1081e4e1ba970100e3dd8000f263688f50d6fcbda3"></a>L4_VCPU_OFFSET_EXT_STATE&#160;</td><td class="fielddoc"><p>Offset where extended state begins. </p>
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<tr><td class="fieldname"><a id="ggaa9c9426f606dfa123ace57a1081e4e1ba51d123b064652c03ed78714ec92615e5" name="ggaa9c9426f606dfa123ace57a1081e4e1ba51d123b064652c03ed78714ec92615e5"></a>L4_VCPU_OFFSET_EXT_INFOS&#160;</td><td class="fielddoc"><p>Offset where extended infos begin. </p>
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<p class="definition">Definition at line <a class="el" href="amd64_2l4_2sys_2____vcpu-arch_8h_source.html#l00034">34</a> of file <a class="el" href="amd64_2l4_2sys_2____vcpu-arch_8h_source.html">__vcpu-arch.h</a>.</p>
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<td class="memname">enum <a class="el" href="#gaa9c9426f606dfa123ace57a1081e4e1b">L4_vcpu_state_offset</a></td>
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<p>Offsets for vCPU state layouts. </p>
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ggaa9c9426f606dfa123ace57a1081e4e1ba970100e3dd8000f263688f50d6fcbda3" name="ggaa9c9426f606dfa123ace57a1081e4e1ba970100e3dd8000f263688f50d6fcbda3"></a>L4_VCPU_OFFSET_EXT_STATE&#160;</td><td class="fielddoc"><p>Offset where extended state begins. </p>
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<tr><td class="fieldname"><a id="ggaa9c9426f606dfa123ace57a1081e4e1ba51d123b064652c03ed78714ec92615e5" name="ggaa9c9426f606dfa123ace57a1081e4e1ba51d123b064652c03ed78714ec92615e5"></a>L4_VCPU_OFFSET_EXT_INFOS&#160;</td><td class="fielddoc"><p>Offset where extended infos begin. </p>
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<p class="definition">Definition at line <a class="el" href="arm_2l4_2sys_2____vcpu-arch_8h_source.html#l00035">35</a> of file <a class="el" href="arm_2l4_2sys_2____vcpu-arch_8h_source.html">__vcpu-arch.h</a>.</p>
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<h2 class="memtitle"><span class="permalink"><a href="#gaa9c9426f606dfa123ace57a1081e4e1b">&#9670;&#160;</a></span>L4_vcpu_state_offset <span class="overload">[3/4]</span></h2>
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<td class="memname">enum <a class="el" href="#gaa9c9426f606dfa123ace57a1081e4e1b">L4_vcpu_state_offset</a></td>
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<p>Offsets for vCPU state layouts. </p>
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ggaa9c9426f606dfa123ace57a1081e4e1ba970100e3dd8000f263688f50d6fcbda3" name="ggaa9c9426f606dfa123ace57a1081e4e1ba970100e3dd8000f263688f50d6fcbda3"></a>L4_VCPU_OFFSET_EXT_STATE&#160;</td><td class="fielddoc"><p>Offset where extended state begins. </p>
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<tr><td class="fieldname"><a id="ggaa9c9426f606dfa123ace57a1081e4e1ba51d123b064652c03ed78714ec92615e5" name="ggaa9c9426f606dfa123ace57a1081e4e1ba51d123b064652c03ed78714ec92615e5"></a>L4_VCPU_OFFSET_EXT_INFOS&#160;</td><td class="fielddoc"><p>Offset where extended infos begin. </p>
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<p class="definition">Definition at line <a class="el" href="arm64_2l4_2sys_2____vcpu-arch_8h_source.html#l00036">36</a> of file <a class="el" href="arm64_2l4_2sys_2____vcpu-arch_8h_source.html">__vcpu-arch.h</a>.</p>
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<td class="memname">enum <a class="el" href="#gaa9c9426f606dfa123ace57a1081e4e1b">L4_vcpu_state_offset</a></td>
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<p>Offsets for vCPU state layouts. </p>
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ggaa9c9426f606dfa123ace57a1081e4e1ba970100e3dd8000f263688f50d6fcbda3" name="ggaa9c9426f606dfa123ace57a1081e4e1ba970100e3dd8000f263688f50d6fcbda3"></a>L4_VCPU_OFFSET_EXT_STATE&#160;</td><td class="fielddoc"><p>Offset where extended state begins. </p>
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<tr><td class="fieldname"><a id="ggaa9c9426f606dfa123ace57a1081e4e1ba51d123b064652c03ed78714ec92615e5" name="ggaa9c9426f606dfa123ace57a1081e4e1ba51d123b064652c03ed78714ec92615e5"></a>L4_VCPU_OFFSET_EXT_INFOS&#160;</td><td class="fielddoc"><p>Offset where extended infos begin. </p>
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<p class="definition">Definition at line <a class="el" href="x86_2l4_2sys_2____vcpu-arch_8h_source.html#l00034">34</a> of file <a class="el" href="x86_2l4_2sys_2____vcpu-arch_8h_source.html">__vcpu-arch.h</a>.</p>
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<h2 class="memtitle"><span class="permalink"><a href="#ga4a26ee99aaf5f75087c6918f57c3d4d5">&#9670;&#160;</a></span>L4_vcpu_sticky_flags</h2>
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<td class="memname">enum <a class="el" href="#ga4a26ee99aaf5f75087c6918f57c3d4d5">L4_vcpu_sticky_flags</a></td>
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<p>Sticky flags of a vCPU. </p>
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga4a26ee99aaf5f75087c6918f57c3d4d5afdc98b96983362771316581981ded160" name="gga4a26ee99aaf5f75087c6918f57c3d4d5afdc98b96983362771316581981ded160"></a>L4_VCPU_SF_IRQ_PENDING&#160;</td><td class="fielddoc"><p>An event is pending: Either an IRQ or another thread attempts to send an IPC to this vCPU thread. </p>
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<p class="definition">Definition at line <a class="el" href="sys_2vcpu_8h_source.html#l00167">167</a> of file <a class="el" href="sys_2vcpu_8h_source.html">vcpu.h</a>.</p>
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