apic.h

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// AUTOMATICALLY GENERATED -- DO NOT EDIT!         -*- c++ -*-

#ifndef apic_h
#define apic_h

#include "types.h"
#include "initcalls.h"

//
// INTERFACE definition follows 
//


class Return_frame;

class Apic
{
public:
  static void init() FIASCO_INIT;

  typedef enum
    {
      APIC_NONE,
      APIC_P6,                  // Intel PPro, PIII
      APIC_P4,                  // Intel PIV
      APIC_K7                   // AMD Athlon Model 2
    } Apic_type;

private:
  Apic();                       // default constructors are undefined
  Apic(const Apic&);
  static void                   error_interrupt(Return_frame *regs)
                                asm ("apic_error_interrupt") FIASCO_FASTCALL;

  static int                    present;
  static int                    good_cpu;
  static const                  Address io_base;
  static Address                phys_base;
  static unsigned               timer_divisor;
  static Apic_type              type;
  static unsigned               frequency_khz;
  static unsigned               max_lvt;
  static Unsigned32             scaler_ns_to_apic;

  enum
    {
      APIC_ID                   = 0x20,
      APIC_LVR                  = 0x30,
      APIC_TASKPRI              = 0x80,
      APIC_TPRI_MASK            = 0xFF,
      APIC_EOI                  = 0xB0,
      APIC_LDR                  = 0xD0,
      APIC_LDR_MASK             = (0xFF<<24),
      APIC_DFR                  = 0xE0,
      APIC_SPIV                 = 0xF0,
      APIC_ISR                  = 0x100,
      APIC_TMR                  = 0x180,
      APIC_IRR                  = 0x200,
      APIC_ESR                  = 0x280,
      APIC_LVTT                 = 0x320,
      APIC_LVTTHMR              = 0x330,
      APIC_LVTPC                = 0x340,
      APIC_LVT0                 = 0x350,
      APIC_TIMER_BASE_DIV       = 0x2,
      APIC_LVT1                 = 0x360,
      APIC_LVTERR               = 0x370,
      APIC_TMICT                = 0x380,
      APIC_TMCCT                = 0x390,
      APIC_TDCR                 = 0x3E0,

      APIC_SND_PENDING          = (1<<12),
      APIC_INPUT_POLARITY       = (1<<13),
      APIC_LVT_REMOTE_IRR       = (1<<14),
      APIC_LVT_LEVEL_TRIGGER    = (1<<15),
      APIC_LVT_MASKED           = (1<<16),
      APIC_LVT_TIMER_PERIODIC   = (1<<17),
      APIC_TDR_DIV_1            = 0xB,
      APIC_TDR_DIV_2            = 0x0,
      APIC_TDR_DIV_4            = 0x1,
      APIC_TDR_DIV_8            = 0x2,
      APIC_TDR_DIV_16           = 0x3,
      APIC_TDR_DIV_32           = 0x8,
      APIC_TDR_DIV_64           = 0x9,
      APIC_TDR_DIV_128          = 0xA,
    };

  enum
    {
      MASK                      =  1,
      TRIGGER_MODE              =  2,
      REMOTE_IRR                =  4,
      PIN_POLARITY              =  8,
      DELIVERY_STATE            = 16,
      DELIVERY_MODE             = 32,
    };

  enum
    {
      APIC_BASE_MSR             = 0x1b,
    };

public:  
  static inline unsigned get_frequency_khz();
  
  static inline Unsigned32 reg_read(unsigned reg);
  
  static inline void reg_write(unsigned reg, Unsigned32 val);
  
  static inline int reg_delivery_mode(Unsigned32 val);
  
  static inline int reg_lvt_vector(Unsigned32 val);
  
  static inline Unsigned32 timer_reg_read();
  
  static inline Unsigned32 timer_reg_read_initial();
  
  static inline void timer_reg_write(Unsigned32 val);
  
  static inline Unsigned32 ns_to_apic(Unsigned64 ns);
  
  static inline void timer_enable_irq();
  
  static inline void timer_disable_irq();
  
  static inline int timer_is_irq_enabled();
  
  static inline void timer_set_periodic();
  
  static inline void timer_set_one_shot();
  
  static inline void timer_assign_irq_vector(unsigned vector);
  
  static inline void irq_ack();
  
  static inline int have_pcint();
  
  static inline int have_tsint();
  
  // give us a hint if we have an APIC but it is disabled
  static int test_present_but_disabled();
  
  // check if we still receive interrupts after we changed the IRQ routing
  static FIASCO_INIT int check_still_getting_interrupts();
  
  static inline int is_present();
  
  static inline int cpu_type();
  
  static void set_perf_nmi();
  
  // deactivate APIC by writing to appropriate MSR
  static void done();
  
  static void reg_show(unsigned reg);
  
  static void regs_show(void);
  
  static void timer_show(void);
  
  static void id_show(void);
  
  static void irr_show();
  
  static void isr_show();

private:  
  static inline Unsigned32 get_id();
  
  static inline Unsigned32 get_version();
  
  static inline int is_integrated();
  
  static inline Unsigned32 get_max_lvt();
  
  static inline Unsigned32 get_num_errors();
  
  static inline void clear_num_errors();
  
  // set the global pagetable entry for the Local APIC device registers
  static FIASCO_INIT void map_apic_page();
  
  // check CPU type if APIC could be present
  static FIASCO_INIT int test_cpu();
  
  // test if APIC present
  static inline int test_present();
  
  static void timer_set_divisor(unsigned newdiv);
  
  static FIASCO_INIT int get_maxlvt();
  
  // check if APIC is working (check timer functionality)
  static FIASCO_INIT int check_working();
  
  static FIASCO_INIT void init_spiv();
  
  // activate APIC error interrupt
  static FIASCO_INIT void enable_errors();
  
  // activate APIC after activating by MSR was successful
  // see "Intel Architecture Software Developer's Manual,
  //      Volume 3: System Programming Guide, Appendix E"
  static FIASCO_INIT void route_pic_through_apic();
  
  static FIASCO_INIT void init_lvt();
  
  // activate APIC by writing to appropriate MSR
  static FIASCO_INIT void activate_by_msr();
  
  static FIASCO_INIT void calibrate_timer();
  
  static const char* reg_lvt_bit_str(unsigned reg, Unsigned32 val, int bit);
  
  static void bitfield_show(unsigned reg, const char *name, char flag);
};

extern unsigned apic_spurious_interrupt_bug_cnt;
extern unsigned apic_spurious_interrupt_cnt;
extern unsigned apic_error_cnt;

//
// IMPLEMENTATION of inline functions (and needed classes)
//




inline unsigned
Apic::get_frequency_khz()
{
  return frequency_khz;
}



inline Unsigned32
Apic::reg_read(unsigned reg)
{
  return *((volatile unsigned*)(io_base + reg));
}



inline void
Apic::reg_write(unsigned reg, Unsigned32 val)
{
  *((volatile Unsigned32*)(io_base + reg)) = val;
}



inline int
Apic::reg_delivery_mode(Unsigned32 val)
{
  return (val >> 8) & 7;
}



inline int
Apic::reg_lvt_vector(Unsigned32 val)
{
  return val & 0xff;
}



inline Unsigned32
Apic::timer_reg_read()
{
  return reg_read(APIC_TMCCT);
}



inline Unsigned32
Apic::timer_reg_read_initial()
{
  return reg_read(APIC_TMICT);
}



inline void
Apic::timer_reg_write(Unsigned32 val)
{
  reg_read(APIC_TMICT);
  reg_write(APIC_TMICT, val);
}



inline Unsigned32
Apic::ns_to_apic(Unsigned64 ns)
{
  Unsigned32 apic, dummy1, dummy2;
  asm ("movl  %%edx, %%ecx              \n\t"
       "mull  %4                        \n\t"
       "movl  %%ecx, %%eax              \n\t"
       "movl  %%edx, %%ecx              \n\t"
       "mull  %4                        \n\t"
       "addl  %%ecx, %%eax              \n\t"
      :"=a" (apic), "=d" (dummy1), "=&c" (dummy2)
      : "A" (ns),   "g" (scaler_ns_to_apic)
       );
  return apic;
}



inline void
Apic::timer_enable_irq()
{
  Unsigned32 tmp_val;

  tmp_val = reg_read(APIC_LVTT);
  tmp_val &= ~(APIC_LVT_MASKED);
  reg_write(APIC_LVTT, tmp_val);
}



inline void
Apic::timer_disable_irq()
{
  Unsigned32 tmp_val;

  tmp_val = reg_read(APIC_LVTT);
  tmp_val |= APIC_LVT_MASKED;
  reg_write(APIC_LVTT, tmp_val);
}



inline int
Apic::timer_is_irq_enabled()
{
  return ~reg_read(APIC_LVTT) & APIC_LVT_MASKED;
}



inline void
Apic::timer_set_periodic()
{
  Unsigned32 tmp_val = reg_read(APIC_LVTT);
  tmp_val |= APIC_LVT_TIMER_PERIODIC;
  reg_write(APIC_LVTT, tmp_val);
}



inline void
Apic::timer_set_one_shot()
{
  Unsigned32 tmp_val = reg_read(APIC_LVTT);
  tmp_val &= ~APIC_LVT_TIMER_PERIODIC;
  reg_write(APIC_LVTT, tmp_val);
}



inline void
Apic::timer_assign_irq_vector(unsigned vector)
{
  Unsigned32 tmp_val = reg_read(APIC_LVTT);
  tmp_val &= 0xffffff00;
  tmp_val |= vector;
  reg_write(APIC_LVTT, tmp_val);
}



inline void
Apic::irq_ack()
{
  reg_read(APIC_SPIV);
  reg_write(APIC_EOI, 0);
}



inline int
Apic::have_pcint()
{
  return (present && (max_lvt >= 4));
}



inline int
Apic::have_tsint()
{
  return (present && (max_lvt >= 5));
}



inline int
Apic::is_present()
{
  return present;
}



inline int
Apic::cpu_type()
{
  return type;
}

#endif // apic_h

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