| activate_by_msr() | Apic | [private, static] |
| Apic() | Apic | [private] |
| Apic(const Apic &) | Apic | [private] |
| APIC_BASE_MSR enum value | Apic | [private] |
| APIC_DFR enum value | Apic | [private] |
| APIC_EOI enum value | Apic | [private] |
| APIC_ESR enum value | Apic | [private] |
| APIC_ID enum value | Apic | [private] |
| APIC_INPUT_POLARITY enum value | Apic | [private] |
| APIC_IRR enum value | Apic | [private] |
| APIC_ISR enum value | Apic | [private] |
| APIC_K7 enum value | Apic | |
| APIC_LDR enum value | Apic | [private] |
| APIC_LDR_MASK enum value | Apic | [private] |
| APIC_LVR enum value | Apic | [private] |
| APIC_LVT0 enum value | Apic | [private] |
| APIC_LVT1 enum value | Apic | [private] |
| APIC_LVT_LEVEL_TRIGGER enum value | Apic | [private] |
| APIC_LVT_MASKED enum value | Apic | [private] |
| APIC_LVT_REMOTE_IRR enum value | Apic | [private] |
| APIC_LVT_TIMER_PERIODIC enum value | Apic | [private] |
| APIC_LVTERR enum value | Apic | [private] |
| APIC_LVTPC enum value | Apic | [private] |
| APIC_LVTT enum value | Apic | [private] |
| APIC_LVTTHMR enum value | Apic | [private] |
| APIC_NONE enum value | Apic | |
| APIC_P4 enum value | Apic | |
| APIC_P6 enum value | Apic | |
| APIC_SND_PENDING enum value | Apic | [private] |
| APIC_SPIV enum value | Apic | [private] |
| APIC_TASKPRI enum value | Apic | [private] |
| APIC_TDCR enum value | Apic | [private] |
| APIC_TDR_DIV_1 enum value | Apic | [private] |
| APIC_TDR_DIV_128 enum value | Apic | [private] |
| APIC_TDR_DIV_16 enum value | Apic | [private] |
| APIC_TDR_DIV_2 enum value | Apic | [private] |
| APIC_TDR_DIV_32 enum value | Apic | [private] |
| APIC_TDR_DIV_4 enum value | Apic | [private] |
| APIC_TDR_DIV_64 enum value | Apic | [private] |
| APIC_TDR_DIV_8 enum value | Apic | [private] |
| APIC_TIMER_BASE_DIV enum value | Apic | [private] |
| APIC_TMCCT enum value | Apic | [private] |
| APIC_TMICT enum value | Apic | [private] |
| APIC_TMR enum value | Apic | [private] |
| APIC_TPRI_MASK enum value | Apic | [private] |
| Apic_type enum name | Apic | |
| bitfield_show(unsigned reg, const char *name, char flag) | Apic | [private, static] |
| calibrate_timer() | Apic | [private, static] |
| check_still_getting_interrupts() | Apic | [static] |
| check_working() | Apic | [private, static] |
| clear_num_errors() | Apic | [inline, private, static] |
| cpu_type() | Apic | [inline, static] |
| DELIVERY_MODE enum value | Apic | [private] |
| DELIVERY_STATE enum value | Apic | [private] |
| done() | Apic | [static] |
| enable_errors() | Apic | [private, static] |
| error_interrupt(Return_frame *regs) asm("apic_error_interrupt") FIASCO_FASTCALL | Apic | [private, static] |
| frequency_khz | Apic | [private, static] |
| get_frequency_khz() | Apic | [inline, static] |
| get_id() | Apic | [inline, private, static] |
| get_max_lvt() | Apic | [inline, private, static] |
| get_maxlvt() | Apic | [private, static] |
| get_num_errors() | Apic | [inline, private, static] |
| get_version() | Apic | [inline, private, static] |
| good_cpu | Apic | [private, static] |
| have_pcint() | Apic | [inline, static] |
| have_tsint() | Apic | [inline, static] |
| id_show(void) | Apic | [static] |
| init() FIASCO_INIT | Apic | [static] |
| init_lvt() | Apic | [private, static] |
| init_spiv() | Apic | [private, static] |
| io_base | Apic | [private, static] |
| irq_ack() | Apic | [inline, static] |
| irr_show() | Apic | [static] |
| is_integrated() | Apic | [inline, private, static] |
| is_present() | Apic | [inline, static] |
| isr_show() | Apic | [static] |
| map_apic_page() | Apic | [private, static] |
| MASK enum value | Apic | [private] |
| max_lvt | Apic | [private, static] |
| ns_to_apic(Unsigned64 ns) | Apic | [inline, static] |
| phys_base | Apic | [private, static] |
| PIN_POLARITY enum value | Apic | [private] |
| present | Apic | [private, static] |
| reg_delivery_mode(Unsigned32 val) | Apic | [inline, static] |
| reg_lvt_bit_str(unsigned reg, Unsigned32 val, int bit) | Apic | [private, static] |
| reg_lvt_vector(Unsigned32 val) | Apic | [inline, static] |
| reg_read(unsigned reg) | Apic | [inline, static] |
| reg_show(unsigned reg) | Apic | [static] |
| reg_write(unsigned reg, Unsigned32 val) | Apic | [inline, static] |
| regs_show(void) | Apic | [static] |
| REMOTE_IRR enum value | Apic | [private] |
| route_pic_through_apic() | Apic | [private, static] |
| scaler_ns_to_apic | Apic | [private, static] |
| set_perf_nmi() | Apic | [static] |
| test_cpu() | Apic | [private, static] |
| test_present() | Apic | [inline, private, static] |
| test_present_but_disabled() | Apic | [static] |
| timer_assign_irq_vector(unsigned vector) | Apic | [inline, static] |
| timer_disable_irq() | Apic | [inline, static] |
| timer_divisor | Apic | [private, static] |
| timer_enable_irq() | Apic | [inline, static] |
| timer_is_irq_enabled() | Apic | [inline, static] |
| timer_reg_read() | Apic | [inline, static] |
| timer_reg_read_initial() | Apic | [inline, static] |
| timer_reg_write(Unsigned32 val) | Apic | [inline, static] |
| timer_set_divisor(unsigned newdiv) | Apic | [private, static] |
| timer_set_one_shot() | Apic | [inline, static] |
| timer_set_periodic() | Apic | [inline, static] |
| timer_show(void) | Apic | [static] |
| TRIGGER_MODE enum value | Apic | [private] |
| type | Apic | [private, static] |
