cpu.h

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// AUTOMATICALLY GENERATED -- DO NOT EDIT!         -*- c++ -*-

#ifndef cpu_h
#define cpu_h

#include "types.h"
#include "initcalls.h"

#include "l4_types.h"
#include "initcalls.h"

//
// INTERFACE definition follows 
//


class Gdt;
class Tss;

class Cpu
{
public:

  enum Vendor
  {
    Vendor_unknown = 0,
    Vendor_intel,
    Vendor_amd,
    Vendor_cyrix,
    Vendor_via,
    Vendor_umc,
    Vendor_nexgen,
    Vendor_rise,
    Vendor_transmeta,
    Vendor_sis,
    Vensor_nsc
  };

  enum CacheTLB
  {
    Cache_unknown = 0,
    Cache_l1_data,
    Cache_l1_inst,
    Cache_l1_trace,
    Cache_l2,
    Cache_l3,
    Tlb_data_4k,
    Tlb_inst_4k,
    Tlb_data_4M,
    Tlb_inst_4M,
    Tlb_data_4k_4M,
    Tlb_inst_4k_4M,
  };

  enum
  {
    Ldt_entry_size = 8,
  };

  enum Local_features
  {
    Lf_rdpmc            = 0x00000001,
    Lf_rdpmc32          = 0x00000002,
  };

  static void                   init();
  static Unsigned64             time_us();
  static int                    can_wrmsr();

private:

  struct Vendor_table {
    Unsigned32                  vendor_mask;
    Unsigned32                  vendor_code;
    Unsigned16                  l2_cache;
    char                        vendor_string[32];
  } __attribute__((packed));

  struct Cache_table {
    Unsigned8                   desc;
    Unsigned8                   level;
    Unsigned16                  size;
    Unsigned8                   asso;
    Unsigned8                   line_size;
  };

  static Unsigned64             _frequency;
  static Unsigned32             _version;
  static Unsigned32             _brand;
  static Unsigned32             _features;
  static Unsigned32             _ext_features;
  static Unsigned32             _ext_amd_features;
  static Unsigned32             _local_features;

  static Unsigned16             _inst_tlb_4k_entries;
  static Unsigned16             _data_tlb_4k_entries;
  static Unsigned16             _inst_tlb_4m_entries;
  static Unsigned16             _data_tlb_4m_entries;
  static Unsigned16             _inst_tlb_4k_4m_entries;
  static Unsigned16             _data_tlb_4k_4m_entries;
  static Unsigned16             _l2_inst_tlb_4k_entries;
  static Unsigned16             _l2_data_tlb_4k_entries;
  static Unsigned16             _l2_inst_tlb_4m_entries;
  static Unsigned16             _l2_data_tlb_4m_entries;

  static Unsigned16             _l1_trace_cache_size;
  static Unsigned16             _l1_trace_cache_asso;

  static Unsigned16             _l1_data_cache_size;
  static Unsigned16             _l1_data_cache_asso;
  static Unsigned16             _l1_data_cache_line_size;

  static Unsigned16             _l1_inst_cache_size;
  static Unsigned16             _l1_inst_cache_asso;
  static Unsigned16             _l1_inst_cache_line_size;

  static Unsigned16             _l2_cache_size;
  static Unsigned16             _l2_cache_asso;
  static Unsigned16             _l2_cache_line_size;

  static Vendor                 _vendor;
  static char                   _model_str[32];

  static Vendor_table const     intel_table[];
  static Vendor_table const     amd_table[];
  static Vendor_table const     cyrix_table[];
  static Vendor_table const     via_table[];
  static Vendor_table const     umc_table[];
  static Vendor_table const     nexgen_table[];
  static Vendor_table const     rise_table[];
  static Vendor_table const     transmeta_table[];
  static Vendor_table const     sis_table[];
  static Vendor_table const     nsc_table[];

  static Cache_table const      intel_cache_table[];

  static char * const                   vendor_ident[];
  static Vendor_table const * const     vendor_table[];

  static Unsigned32             scaler_tsc_to_ns;
  static Unsigned32             scaler_tsc_to_us;
  static Unsigned32             scaler_ns_to_tsc;
private:

public:
  enum Lbr
    {
      LBR_UNINITIALIZED = 0,
      LBR_NONE,
      LBR_P6,
      LBR_P4,
    };

private:
  static Lbr            lbr                     asm ("CPU_LBR");
  typedef void          (Sysenter)(void);
  static Sysenter       *current_sysenter       asm ("CURRENT_SYSENTER");
  static Gdt            *gdt                    asm ("CPU_GDT");
  static Tss            *tss                    asm ("CPU_TSS");
  static Tss            *tss_dbf;

public:  
  static inline char const * vendor_str();
  
  static inline char const* model_str();
  
  static inline Cpu::Vendor const vendor();
  
  static inline unsigned int const family();
  
  static inline unsigned int const model();
  
  static inline unsigned int const stepping();
  
  static inline unsigned int const type();
  
  static inline Unsigned64 frequency();
  
  static inline unsigned int const brand();
  
  static inline unsigned int const features();
  
  static inline unsigned int const ext_features();
  
  static inline unsigned int const ext_amd_features();
  
  static inline unsigned int const local_features();
  
  static inline bool have_superpages();
  
  static inline bool have_tsc();
  
  static inline bool have_sysenter();
  
  static FIASCO_INIT void identify();
  
  static inline Unsigned32 muldiv(Unsigned32 val, Unsigned32 mul, Unsigned32 div);
  
  static inline Unsigned64 ns_to_tsc(Unsigned64 ns);
  
  static inline Unsigned64 tsc_to_ns(Unsigned64 tsc);
  
  static inline Unsigned64 tsc_to_us(Unsigned64 tsc);
  
  static inline void tsc_to_s_and_ns(Unsigned64 tsc, Unsigned32 *s, Unsigned32 *ns);
  
  static inline void busy_wait_ns(Unsigned64 ns);
  
  static inline Unsigned64 rdtsc(void);
  
  static inline Unsigned32 get_scaler_tsc_to_ns();
  
  static inline Unsigned32 get_scaler_tsc_to_us();
  
  static inline Unsigned32 get_scaler_ns_to_tsc();
  
  static inline Unsigned32 get_flags();
  
  static inline void set_flags(Unsigned32 efl);
  
  static inline Unsigned32 get_es();
  
  static inline Unsigned32 get_ss();
  
  static inline Unsigned32 get_fs();
  
  static inline Unsigned32 get_gs();
  
  static inline void set_ds(Unsigned32 val);
  
  static inline void set_es(Unsigned32 val);
  
  static inline void set_fs(Unsigned32 val);
  
  static inline void set_gs(Unsigned32 val);
  
  static void show_cache_tlb_info(const char *indent);
  
  static inline void memcpy_bytes(void *dst, void const *src, size_t n);
  
  static inline void memcpy_mwords(void *dst, void const *src, size_t n);
  
  static inline void memcpy_bytes_fs(void *dst, void const *src, size_t n);
  
  static inline void memcpy_mwords_fs(void *dst, void const *src, size_t n);
  
  static inline void set_cr0(Unsigned32 val);
  
  static inline void set_pdbr(Address addr);
  
  static inline void set_cr4(Unsigned32 val);
  
  static inline void set_ldt(Unsigned16 val);
  
  static inline void set_cs();
  
  static inline void set_ss(Unsigned32 val);
  
  static inline void set_tr(Unsigned16 val);
  
  static inline Mword get_cr0();
  
  static inline Address get_pdbr();
  
  static inline Mword get_cr4();
  
  static inline Unsigned16 get_ldt();
  
  static inline Unsigned16 get_tr();
  
  static inline Unsigned64 rdmsr(Unsigned32 reg);
  
  static inline Unsigned64 rdpmc(Unsigned32 idx, Unsigned32);
  
  static inline void wrmsr(Unsigned32 low, Unsigned32 high, Unsigned32 reg);
  
  static inline void wrmsr(Unsigned64 msr, Unsigned32 reg);
  
  static inline void enable_rdpmc();
  
  static Cpu::Lbr const lbr_type();
  
  static inline void enable_lbr(void);
  
  static inline void disable_lbr(void);
  
  static FIASCO_INIT void init_sysenter(Address kernel_esp);
  
  static void set_sysenter(void (*func)(void));
  
  static void get_sysenter(void (**func)(void));
  
  static FIASCO_INIT void init_gdt(Address gdt_mem, Address user_max);
  
  static FIASCO_INIT void init_tss(Address tss_mem, size_t tss_size);
  
  static FIASCO_INIT void init_tss_dbf(Address tss_dbf_mem, Address kdir);
  
  static inline void set_gdt();
  
  static inline void set_tss();
  
  static inline Gdt* get_gdt();
  
  static inline Tss* get_tss();
  
  static inline void enable_ldt(Address addr, int size);

private:  
  static inline FIASCO_INIT void cpuid(Unsigned32 const mode, Unsigned32 *const eax, Unsigned32 *const ebx, Unsigned32 *const ecx, Unsigned32 *const edx);
  
  static FIASCO_INIT void cache_tlb_intel();
  
  static FIASCO_INIT void cache_tlb_l1();
  
  static FIASCO_INIT void cache_tlb_l2(Cpu::Vendor vendor);
  
  static FIASCO_INIT void set_model_str(Cpu::Vendor const vendor, unsigned const version, Unsigned16 const l2_cache);
  
  // Return 2^32 / (tsc clocks per usec)
  static FIASCO_INIT void calibrate_tsc();
};
/*
 * Fiasco ia32-native
 * Architecture specific cpu init code
 */


//
// IMPLEMENTATION includes follow (for use by inline functions)
//

#include "gdt.h"
#include "processor.h"
#include "regdefs.h"

//
// IMPLEMENTATION of inline functions (and needed classes)
//




inline char const *
Cpu::vendor_str()
{
  return _vendor == Vendor_unknown ? "Unknown" : vendor_ident[_vendor];
}



inline char const*
Cpu::model_str()
{ return _model_str; }



inline Cpu::Vendor const
Cpu::vendor()
{ return _vendor; }



inline unsigned int const
Cpu::family()
{
  unsigned int val = (_version >> 8) & 0xF;

  return val == 0xF ? val + ((_version >> 16) & 0xF0) : val;
}



inline unsigned int const
Cpu::model()
{
  unsigned int val = (_version >> 4) & 0xF;

  return val == 0xF ? val + ((_version >> 12) & 0xF0) : val;
}



inline unsigned int const
Cpu::stepping()
{ return _version & 0xF; }



inline unsigned int const
Cpu::type()
{ return (_version >> 12) & 0x3; }



inline Unsigned64
Cpu::frequency()
{ return _frequency; }



inline unsigned int const
Cpu::brand()
{ return _brand & 0xFF; }



inline unsigned int const
Cpu::features()
{ return _features; }



inline unsigned int const
Cpu::ext_features()
{ return _ext_features; }



inline unsigned int const
Cpu::ext_amd_features()
{ return _ext_amd_features; }



inline unsigned int const
Cpu::local_features()
{ return _local_features; }



inline bool
Cpu::have_superpages()
{ return features() & FEAT_PSE; }



inline bool
Cpu::have_tsc()
{ return features() & FEAT_TSC; }



inline bool
Cpu::have_sysenter()
{ return features() & FEAT_SEP; }



inline Unsigned32
Cpu::muldiv(Unsigned32 val, Unsigned32 mul, Unsigned32 div)
{
  Unsigned32 dummy;

  asm volatile ("mull %3 ; divl %4\n\t"
               :"=a" (val), "=d" (dummy)
               : "0" (val),  "d" (mul),  "c" (div));
  return val;
}



inline Unsigned64
Cpu::ns_to_tsc(Unsigned64 ns)
{
  Unsigned32 dummy;
  Unsigned64 tsc;
  asm volatile
        ("movl  %%edx, %%ecx            \n\t"
         "mull  %3                      \n\t"
         "movl  %%ecx, %%eax            \n\t"
         "movl  %%edx, %%ecx            \n\t"
         "mull  %3                      \n\t"
         "addl  %%ecx, %%eax            \n\t"
         "adcl  $0, %%edx               \n\t"
         "shld  $5, %%eax, %%edx        \n\t"
         "shll  $5, %%eax               \n\t"
        :"=A" (tsc), "=c" (dummy)
        : "0" (ns),  "b" (scaler_ns_to_tsc)
        );
  return tsc;
}



inline Unsigned64
Cpu::tsc_to_ns(Unsigned64 tsc)
{
  Unsigned32 dummy;
  Unsigned64 ns;
  asm volatile
        ("movl  %%edx, %%ecx            \n\t"
         "mull  %3                      \n\t"
         "movl  %%ecx, %%eax            \n\t"
         "movl  %%edx, %%ecx            \n\t"
         "mull  %3                      \n\t"
         "addl  %%ecx, %%eax            \n\t"
         "adcl  $0, %%edx               \n\t"
         "shld  $5, %%eax, %%edx        \n\t"
         "shll  $5, %%eax               \n\t"
        :"=A" (ns), "=c" (dummy)
        : "0" (tsc), "b" (scaler_tsc_to_ns)
        );
  return ns;
}



inline Unsigned64
Cpu::tsc_to_us(Unsigned64 tsc)
{
  Unsigned32 dummy;
  Unsigned64 us;
  asm volatile
        ("movl  %%edx, %%ecx            \n\t"
         "mull  %3                      \n\t"
         "movl  %%ecx, %%eax            \n\t"
         "movl  %%edx, %%ecx            \n\t"
         "mull  %3                      \n\t"
         "addl  %%ecx, %%eax            \n\t"
         "adcl  $0, %%edx               \n\t"
        :"=A" (us), "=c" (dummy)
        : "0" (tsc), "S" (scaler_tsc_to_us)
        );
  return us;
}



inline void
Cpu::tsc_to_s_and_ns(Unsigned64 tsc, Unsigned32 *s, Unsigned32 *ns)
{
    Unsigned32 dummy;
    __asm__
        ("                              \n\t"
         "movl  %%edx, %%ecx            \n\t"
         "mull  %4                      \n\t"
         "movl  %%ecx, %%eax            \n\t"
         "movl  %%edx, %%ecx            \n\t"
         "mull  %4                      \n\t"
         "addl  %%ecx, %%eax            \n\t"
         "adcl  $0, %%edx               \n\t"
         "movl  $1000000000, %%ecx      \n\t"
         "shld  $5, %%eax, %%edx        \n\t"
         "shll  $5, %%eax               \n\t"
         "divl  %%ecx                   \n\t"
        :"=a" (*s), "=d" (*ns), "=c" (dummy)
        : "A" (tsc), "g" (scaler_tsc_to_ns)
        );
}



inline void
Cpu::busy_wait_ns(Unsigned64 ns)
{
  Unsigned64 stop = rdtsc () + ns_to_tsc(ns);

  while (rdtsc() < stop)
    Proc::pause();
}



inline Unsigned64
Cpu::rdtsc(void)
{
  Unsigned64 tsc;
  asm volatile ("rdtsc" : "=A" (tsc));
  return tsc;
}



inline Unsigned32
Cpu::get_scaler_tsc_to_ns()
{ return scaler_tsc_to_ns; }



inline Unsigned32
Cpu::get_scaler_tsc_to_us()
{ return scaler_tsc_to_us; }



inline Unsigned32
Cpu::get_scaler_ns_to_tsc()
{ return scaler_ns_to_tsc; }



inline Unsigned32
Cpu::get_flags()
{ Unsigned32 efl; asm volatile ("pushfl ; popl %0" : "=rm"(efl)); return efl; }



inline void
Cpu::set_flags(Unsigned32 efl)
{ asm volatile ("pushl %0 ; popfl" : : "rm" (efl) : "memory"); }



inline Unsigned32
Cpu::get_es()
{ Unsigned32 val; asm volatile ("mov %%es, %0" : "=rm" (val)); return val; }



inline Unsigned32
Cpu::get_ss()
{ Unsigned32 val; asm volatile ("mov %%ss, %0" : "=rm" (val)); return val; }



inline Unsigned32
Cpu::get_fs()
{ Unsigned32 val; asm volatile ("mov %%fs, %0" : "=rm" (val)); return val; }



inline Unsigned32
Cpu::get_gs()
{ Unsigned32 val; asm volatile ("mov %%gs, %0" : "=rm" (val)); return val; }



inline void
Cpu::set_ds(Unsigned32 val)
{ asm volatile ("mov %0, %%ds" : : "rm" (val)); }



inline void
Cpu::set_es(Unsigned32 val)
{ asm volatile ("mov %0, %%es" : : "rm" (val)); }



inline void
Cpu::set_fs(Unsigned32 val)
{ asm volatile ("mov %0, %%fs" : : "rm" (val)); }



inline void
Cpu::set_gs(Unsigned32 val)
{ asm volatile ("mov %0, %%gs" : : "rm" (val)); }



inline void
Cpu::memcpy_bytes(void *dst, void const *src, size_t n)
{
  unsigned dummy1, dummy2, dummy3;

  asm volatile ("cld                                    \n\t"
                "repz movsl %%ds:(%%esi), %%es:(%%edi)  \n\t"
                "mov %%edx, %%ecx                       \n\t"
                "repz movsb %%ds:(%%esi), %%es:(%%edi)  \n\t"
                : "=c" (dummy1), "=S" (dummy2), "=D" (dummy3)
                : "c" (n >> 2), "d" (n & 3), "S" (src), "D" (dst)
                : "memory");
}



inline void
Cpu::memcpy_mwords(void *dst, void const *src, size_t n)
{
  unsigned dummy1, dummy2, dummy3;

  asm volatile ("cld                                    \n\t"
                "rep movsl %%ds:(%%esi), %%es:(%%edi)   \n\t"
                : "=c" (dummy1), "=S" (dummy2), "=D" (dummy3)
                : "c" (n), "S" (src), "D" (dst)
                : "memory");
}



inline void
Cpu::memcpy_bytes_fs(void *dst, void const *src, size_t n)
{
  unsigned dummy1, dummy2, dummy3;

  asm volatile ("cld                                    \n\t"
                "rep movsl %%fs:(%%esi), %%es:(%%edi)   \n\t"
                "mov %%edx, %%ecx                       \n\t"
                "repz movsb %%fs:(%%esi), %%es:(%%edi)  \n\t"
                : "=c" (dummy1), "=S" (dummy2), "=D" (dummy3)
                : "c" (n >> 2), "d" (n & 3), "S" (src), "D" (dst)
                : "memory");
}



inline void
Cpu::memcpy_mwords_fs(void *dst, void const *src, size_t n)
{
  unsigned dummy1, dummy2, dummy3;

  asm volatile ("cld                                    \n\t"
                "rep movsl %%fs:(%%esi), %%es:(%%edi)   \n\t"
                : "=c" (dummy1), "=S" (dummy2), "=D" (dummy3)
                : "c" (n), "S" (src), "D" (dst)
                : "memory");
}



inline void
Cpu::set_cr0(Unsigned32 val)
{ asm volatile ("movl %0, %%cr0" : : "r" (val)); }



inline void
Cpu::set_pdbr(Address addr)
{ asm volatile ("movl %0, %%cr3" : : "r" (addr)); }



inline void
Cpu::set_cr4(Unsigned32 val)
{ asm volatile ("movl %0, %%cr4" : : "r" (val)); }



inline void
Cpu::set_ldt(Unsigned16 val)
{ asm volatile ("lldt %0" : : "rm" (val)); }



inline void
Cpu::set_cs()
{
  asm volatile ("ljmp %0,$1f ; 1:" 
                : : "i"(Gdt::gdt_code_kernel | Gdt::Selector_kernel));
}



inline void
Cpu::set_ss(Unsigned32 val)
{ asm volatile ("movl %0, %%ss" : : "rm" (val)); }



inline void
Cpu::set_tr(Unsigned16 val)
{ asm volatile ("ltr %0" : : "rm" (val)); }



inline Mword
Cpu::get_cr0()
{ Mword val; asm volatile ("movl %%cr0, %0" : "=r" (val)); return val; }



inline Address
Cpu::get_pdbr()
{ Address addr; asm volatile ("movl %%cr3, %0" : "=r" (addr)); return addr; }



inline Mword
Cpu::get_cr4()
{ Mword val; asm volatile ("movl %%cr4, %0" : "=r" (val)); return val; }



inline Unsigned16
Cpu::get_ldt()
{ Unsigned16 val; asm volatile ("sldt %0" : "=rm" (val)); return val; }



inline Unsigned16
Cpu::get_tr()
{ Unsigned16 val; asm volatile ("str %0" : "=rm" (val)); return val; }



inline Unsigned64
Cpu::rdmsr(Unsigned32 reg)
{
  Unsigned64 msr;

  asm volatile ("rdmsr" : "=A" (msr) : "c" (reg));
  return msr;
}



inline Unsigned64
Cpu::rdpmc(Unsigned32 idx, Unsigned32)
{
  Unsigned64 pmc;

  asm volatile ("rdpmc" : "=A" (pmc) : "c" (idx));
  return pmc;
}



inline void
Cpu::wrmsr(Unsigned32 low, Unsigned32 high, Unsigned32 reg)
{ asm volatile ("wrmsr" : : "a" (low), "d" (high), "c" (reg)); }



inline void
Cpu::wrmsr(Unsigned64 msr, Unsigned32 reg)
{ asm volatile ("wrmsr" : : "A" (msr), "c" (reg)); }



inline void
Cpu::enable_rdpmc()
{ set_cr4(get_cr4() | CR4_PCE); }



inline void
Cpu::enable_lbr(void)
{
  if (lbr_type() != LBR_NONE)
    {
      Unsigned64 lbr_ctrl = rdmsr (0x1d9);
      wrmsr (lbr_ctrl | 1, 0x1d9);
    }
}



inline void
Cpu::disable_lbr(void)
{
  if (lbr_type() != LBR_NONE)
    {
      Unsigned64 lbr_ctrl = rdmsr (0x1d9);
      wrmsr (lbr_ctrl & ~1, 0x1d9);
    }
}



inline void
Cpu::set_gdt()
{
  Pseudo_descriptor desc((Address)gdt, Gdt::gdt_max-1);
  Gdt::set (&desc);
}



inline void
Cpu::set_tss()
{
  set_tr (Gdt::gdt_tss);
}



inline Gdt*
Cpu::get_gdt()
{ return gdt; }



inline Tss*
Cpu::get_tss()
{ return tss; }



inline void
Cpu::enable_ldt(Address addr, int size)
{
  if (!size)
    {
      get_gdt()->clear_entry (Gdt::gdt_ldt / 8);
      set_ldt(0);
    }
  else
    {
      get_gdt()->set_entry_byte (Gdt::gdt_ldt / 8, addr, size-1, 2/*=ldt*/, 0);
      set_ldt(Gdt::gdt_ldt);
    }
}



inline int
Cpu::can_wrmsr()
{ return features() & FEAT_MSR; }



inline Unsigned64
Cpu::time_us()
{
  return tsc_to_us (rdtsc());
}

#endif // cpu_h

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