perf_cnt.h

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// AUTOMATICALLY GENERATED -- DO NOT EDIT!         -*- c++ -*-

#ifndef perf_cnt_h
#define perf_cnt_h

#include "types.h"

#include "cpu.h"
#include "types.h"

//
// INTERFACE definition follows 
//


class Perf_cnt_arch;

class Perf_cnt
{
public:
  enum {
    Max_slot = 2,
    Max_pmc  = 4,
  };

  enum Unit_mask_type
    { None, Fixed, Exclusive, Bitmask, };

  typedef Mword (*Perf_read_fn)();
private:

public:
  enum Perf_event_type
    { P5, P6, P4, };

  static Perf_read_fn read_pmc[Max_slot];

private:
  static Perf_read_fn *read_pmc_fns;
  static Perf_read_fn read_pmc_fn[Max_slot];
  static Perf_cnt_arch *pcnt;
  static char const *perf_type_str;
  static Perf_event_type perf_event_type;

public:  
  // basic perfcounter detection
  static FIASCO_INIT void init();
  
  static inline void set_pmc_fn(Mword slot, Mword nr);
  
  // watchdog supported by performance counter architecture?
  static inline int have_watchdog();
  
  // setup watchdog function with timeout in seconds
  static inline void setup_watchdog(Mword timeout);
  
  static inline void setup_loadcnt();
  
  static inline void start_watchdog();
  
  static inline void stop_watchdog();
  
  static inline void touch_watchdog();
  
  // return human-readable type of performance counters
  static inline char const * perf_type();
  
  // set performance counter counting the selected event in slot #slot
  static int setup_pmc(Mword slot, Mword event, Mword user, Mword kern, Mword edge);
  
  // return current selected event for a slot #slot
  static int mode(Mword slot, const char **mode, const char **name, Mword *event, Mword *user, Mword *kern, Mword *edge);
  
  static Mword get_max_perf_event();
  
  static void get_perf_event(Mword nr, unsigned *evntsel, const char **name, const char **desc);
  
  static Mword lookup_event(unsigned evntsel);
  
  static void get_unit_mask(Mword nr, Unit_mask_type *type, Mword *default_value, Mword *nvalues);
  
  static void get_unit_mask_entry(Mword nr, Mword idx, Mword *value, const char **desc);
  
  static void split_event(Mword event, unsigned *evntsel, Mword *unit_mask);
  
  static void combine_event(Mword evntsel, Mword unit_mask, Mword *event);
};

class Perf_cnt_arch
{
public:
  // basic initialization
  virtual int  init() = 0;

  // set event the counter should count
  virtual void set_pmc_event(Mword slot) = 0;

  inline void touch_watchdog()
    { Cpu::wrmsr(hold_watchdog, _ctr_reg0+pmc_watchdog); }

protected:
  Mword _nr_regs;
  Mword _sel_reg0;
  Mword _ctr_reg0;
  Mword _watchdog;

  typedef struct 
  {
    char  user;         // 1=count in user mode
    char  kern;         // 1=count in kernel mode
    char  edge;         // 1=count edge / 0=count duration
    Mword pmc;          // # of performance counter
    Mword bitmask;      // counter bitmask
    Mword evnt;         // event selector
  } Event;

  static Mword    pmc_watchdog;                   // # perfcounter of watchdog
  static Mword    pmc_loadcnt;                    // # perfcounter of loadcnt
  static Signed64 hold_watchdog;
  static Event    pmc_event[Perf_cnt::Max_slot];  // index is slot number
  static char     pmc_alloc[Perf_cnt::Max_pmc];   // index is # of perfcounter

public:  
  inline Mword watchdog_allocated();
  
  inline Mword loadcnt_allocated();
  
  virtual void clear_pmc(Mword reg_nr);
  
  void mode(Mword slot, const char **mode, Mword *event, Mword *user, Mword *kern, Mword *edge);
  
  void setup_pmc(Mword slot, Mword bitmask, Mword event, Mword user, Mword kern, Mword edge);
  
  virtual void start_pmc(Mword /*reg_nr*/);
  
  // watchdog supported by performance counter architecture?
  inline int have_watchdog();
  
  void setup_watchdog(Mword timeout);
  
  void setup_loadcnt();
  
  virtual void init_watchdog();
  
  virtual void init_loadcnt();
  
  // start watchdog (enable generation of overflow interrupt)
  virtual void start_watchdog();
  
  // stop watchdog (disable generation of overflow interrupt)
  virtual void stop_watchdog();

protected:  
  //--------------------------------------------------------------------
  inline Perf_cnt_arch(Mword sel_reg0, Mword ctr_reg0, Mword nr_regs, Mword watchdog);

private:  
  void alloc_watchdog();
  
  void alloc_loadcnt();
  
  // allocate a performance counter according to bitmask (some events depend
  // on specific counters)
  int alloc_pmc(Mword slot, Mword bitmask);
};

class Perf_cnt_p5 : public Perf_cnt_arch {
public:  
  //--------------------------------------------------------------------
  // Intel P5 (Pentium/Pentium MMX) has 2 performance counters. No overflow
  // interrupt available. Some events are not symmtetric.
  inline Perf_cnt_p5();

private:  
  FIASCO_INIT int init();
  
  void set_pmc_event(Mword slot);
};
class Perf_cnt_p6 : public Perf_cnt_arch {
public:  
  //--------------------------------------------------------------------
  // Intel P6 (PPro/PII/PIII) has 2 performance counters. Overflow interrupt
  // is available. Some events are not symmtetric.
  inline Perf_cnt_p6();

protected:  
  Perf_cnt_p6(Mword sel_reg0, Mword ctr_reg0, Mword nr_regs, Mword watchdog);

private:  
  FIASCO_INIT int init();
  
  void set_pmc_event(Mword slot);
  
  void start_pmc(Mword /*reg_nr*/);
  
  void init_watchdog();
  
  void init_loadcnt();
  
  void start_watchdog();
  
  void stop_watchdog();
};
class Perf_cnt_k7 : public Perf_cnt_p6   {
public:  
  //--------------------------------------------------------------------
  // AMD K7 (Athlon, K8=Athlon64) has 4 performance counters. All events
  // seem to be symmtetric. Overflow interrupts available.
  inline Perf_cnt_k7();

private:  
  void start_pmc(Mword reg_nr);
  
  void init_watchdog();
  
  void init_loadcnt();
};
class Perf_cnt_p4 : public Perf_cnt_arch {
public:  
  //--------------------------------------------------------------------
  // Intel P4
  inline Perf_cnt_p4();

private:  
  static inline Mword escr_event_select(Mword n);
  
  static inline Mword escr_event_mask(Mword n);
  
  static inline Mword cccr_threshold(Mword n);
  
  static inline Mword cccr_escr_select(Mword n);
  
  FIASCO_INIT int init();
  
  void set_pmc_event(Mword /*slot*/);
  
  void start_pmc(Mword reg_nr);
  
  void init_watchdog();
  
  void init_loadcnt();
  
  void start_watchdog();
  
  void stop_watchdog();
};

//
// IMPLEMENTATION of inline functions (and needed classes)
//



// watchdog supported by performance counter architecture?

inline int
Perf_cnt::have_watchdog()
{ return (pcnt && pcnt->have_watchdog()); }


// setup watchdog function with timeout in seconds

inline void
Perf_cnt::setup_watchdog(Mword timeout)
{
  if (pcnt)
    pcnt->setup_watchdog(timeout);
}



inline void
Perf_cnt::setup_loadcnt()
{
  if (pcnt)
    pcnt->setup_loadcnt();
}



inline void
Perf_cnt::start_watchdog()
{
  if (pcnt && pcnt->watchdog_allocated())
    {
      pcnt->touch_watchdog();
      pcnt->start_watchdog();
    }
}



inline void
Perf_cnt::stop_watchdog()
{
  if (pcnt && pcnt->watchdog_allocated())
    pcnt->stop_watchdog();
}



inline void
Perf_cnt::touch_watchdog()
{
  if (pcnt && pcnt->watchdog_allocated())
    pcnt->touch_watchdog();
}


// return human-readable type of performance counters

inline char const *
Perf_cnt::perf_type()
{ return perf_type_str; }



inline Mword
Perf_cnt_arch::watchdog_allocated()
{ return (pmc_watchdog != (Mword)-1); }



inline Mword
Perf_cnt_arch::loadcnt_allocated()
{ return (pmc_loadcnt != (Mword)-1); }


// watchdog supported by performance counter architecture?

inline int
Perf_cnt_arch::have_watchdog()
{ return _watchdog; }



//--------------------------------------------------------------------

inline Perf_cnt_arch::Perf_cnt_arch(Mword sel_reg0, Mword ctr_reg0, 
                             Mword nr_regs, Mword watchdog)
{
  _sel_reg0 = sel_reg0;
  _ctr_reg0 = ctr_reg0;
  _nr_regs  = nr_regs;
  _watchdog = watchdog;

  for (Mword slot=0; slot<Perf_cnt::Max_slot; slot++)
    {
      pmc_event[slot].pmc  = (Mword)-1;
      pmc_event[slot].edge = 0;
    }
}

#endif // perf_cnt_h

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