uart_registers.hpp

00001 #if !defined(__UART_REGISTERS_HPP__)
00002 #define __UART_REGISTERS_HPP__
00003 
00004 //
00005 // local includes
00006 //
00007 #include "devices/common.hpp"
00008 
00016 struct uart_registers                                   // no register block
00017 {
00018     enum interrupt_ids
00019     {
00020         //
00021         // 3  2  1  Prio  Description
00022         // 0  1  1  1     Received Error (OE, PE, BI, or FE)
00023         // 0  1  0  2     Received Data Available
00024         // 1  1  0  2     Trigger level identification (Stale data in receive buffer)
00025         // 0  0  1  3     Transmitter has room for more words (THRE)
00026         // 0  0  0  4     Modem Status Change (-CTS, -DSR, -RI, or -DCD)
00027         //
00028         RECEIVED_ERROR               = 0x03,
00029         RECEIVED_DATA_AVAILABLE      = 0x02,
00030         TRIGGER_LEVEL_IDENTIFICATION = 0x06,            // not applicable on 8250/16450 UARTs
00031         THR_EMPTY                    = 0x01,
00032         MODEM_STATUS_CHANGE          = 0x00
00033     };
00034 
00035     //
00036     // Receive Buffer Register (RBR) (read) & Transmit Holding Register (THR) (write),
00037     //     if lcr.divisor_latch_access == 0 at offset: 0x00
00038     //
00039     uint8_t rbr, thr;
00040 
00041     //
00042     // Interrupt Enable Register (IER) (read-write),
00043     //     if lcr.divisor_latch_access == 0 at offset: 0x01
00044     //
00045     union ier
00046     {
00047         uint8_t raw;
00048 
00049         struct __packed()
00050         {
00051           #if LITTLE_ENDIAN_BITFIELD
00052             unsigned received_data_available      : 1;  // bit 0
00053             unsigned thr_empty                    : 1;  // bit 1
00054             unsigned receiver_line_status         : 1;  // bit 2
00055             unsigned modem_status                 : 1;  // bit 3
00056             unsigned reserved4_7                  : 4;  // bit 4-7
00057           #elif BIG_ENDIAN_BITFIELD
00058             unsigned reserved4_7                  : 4;  // bit 4-7
00059             unsigned modem_status                 : 1;  // bit 3
00060             unsigned receiver_line_status         : 1;  // bit 2
00061             unsigned thr_empty                    : 1;  // bit 1
00062             unsigned received_data_available      : 1;  // bit 0
00063           #else
00064             #error unknown bitfield order. fix this.
00065           #endif
00066         };
00067 
00068         ACCESS_FUNCTORS(ier&, uint8_t, raw)
00069         NUMERIC_ACCESS_OPERATORS(ier&, uint8_t, raw)
00070         INCREMENT_OPERATORS(ier, raw)
00071     } ier;
00072 
00073     //
00074     // Divisor Latch LSB (DLL) & Divisor Latch MSB (DLH) (read-write),
00075     //     if lcr.divisor_latch_access == 1 at offsets: 0x00 & 0x01
00076     //
00077     uint16_t divisor_latch;
00078 
00079     //
00080     // Interrupt Identification Register (IIR) (read) at offset: 0x02
00081     //
00082     union iir
00083     {
00084         uint8_t raw;
00085 
00086         struct __packed()
00087         {
00088           #if LITTLE_ENDIAN_BITFIELD
00089             unsigned no_interrupt_pending         : 1;  // bit 0
00090             unsigned interrupt_id                 : 3;  // bit 1-3 (3 is 0 on 8250/16450 UARTs)
00091             unsigned reserved4_5                  : 2;  // bit 4-5
00092             unsigned fifos_enabled0               : 1;  // bit 6
00093             unsigned fifos_enabled1               : 1;  // bit 7
00094           #elif BIG_ENDIAN_BITFIELD
00095             unsigned fifos_enabled1               : 1;  // bit 7
00096             unsigned fifos_enabled0               : 1;  // bit 6
00097             unsigned reserved4_5                  : 2;  // bit 4-5
00098             unsigned interrupt_id                 : 3;  // bit 1-3 (3 is 0 on 8250/16450 UARTs)
00099             unsigned no_interrupt_pending         : 1;  // bit 0
00100           #else
00101             #error unknown bitfield order. fix this.
00102           #endif
00103         };
00104 
00105         ACCESS_FUNCTORS(iir&, uint8_t, raw)
00106         NUMERIC_ACCESS_OPERATORS(iir&, uint8_t, raw)
00107         INCREMENT_OPERATORS(iir, raw)
00108     } iir;
00109 
00110     //
00111     // FIFO Control Register (FCR) (write) at offset: 0x02
00112     //     (does not exist on 8250/16450 UARTs)
00113     //
00114 
00115     //
00116     // Line Control Register (LCR) (read-write) at offset: 0x03
00117     //
00118     union lcr
00119     {
00120         uint8_t raw;
00121 
00122         struct __packed()
00123         {
00124           #if LITTLE_ENDIAN_BITFIELD
00125             unsigned data_bits                    : 2;  // bit 0-1 (computes as bits + 5)
00126             unsigned stop_bits                    : 1;  // bit 2
00127             unsigned enable_parity                : 1;  // bit 3
00128             unsigned even_parity                  : 1;  // bit 4
00129             unsigned sticky_parity                : 1;  // bit 5
00130             unsigned break_control                : 1;  // bit 6
00131             unsigned divisor_latch_access         : 1;  // bit 7
00132           #elif BIG_ENDIAN_BITFIELD
00133             unsigned divisor_latch_access         : 1;  // bit 7
00134             unsigned break_control                : 1;  // bit 6
00135             unsigned sticky_parity                : 1;  // bit 5
00136             unsigned even_parity                  : 1;  // bit 4
00137             unsigned enable_parity                : 1;  // bit 3
00138             unsigned stop_bits                    : 1;  // bit 2
00139             unsigned data_bits                    : 2;  // bit 0-1 (computes as bits + 5)
00140           #else
00141             #error unknown bitfield order. fix this.
00142           #endif
00143         };
00144 
00145         ACCESS_FUNCTORS(lcr&, uint8_t, raw)
00146         NUMERIC_ACCESS_OPERATORS(lcr&, uint8_t, raw)
00147         INCREMENT_OPERATORS(lcr, raw)
00148     } lcr;
00149 
00150     //
00151     // Modem Control Register (MCR) (read-write) at offset: 0x04
00152     //
00153     union mcr
00154     {
00155         uint8_t raw;
00156 
00157         struct __packed()
00158         {
00159           #if LITTLE_ENDIAN_BITFIELD
00160             unsigned data_terminal_ready          : 1;  // bit 0
00161             unsigned request_to_send              : 1;  // bit 1
00162             unsigned out1                         : 1;  // bit 2
00163             unsigned out2                         : 1;  // bit 3
00164             unsigned enable_loopback              : 1;  // bit 4
00165             unsigned reserved5_7                  : 3;  // bit 5-7
00166           #elif BIG_ENDIAN_BITFIELD
00167             unsigned reserved5_7                  : 3;  // bit 5-7
00168             unsigned enable_loopback              : 1;  // bit 4
00169             unsigned out2                         : 1;  // bit 3
00170             unsigned out1                         : 1;  // bit 2
00171             unsigned request_to_send              : 1;  // bit 1
00172             unsigned data_terminal_ready          : 1;  // bit 0
00173           #else
00174             #error unknown bitfield order. fix this.
00175           #endif
00176         };
00177 
00178         ACCESS_FUNCTORS(mcr&, uint8_t, raw)
00179         NUMERIC_ACCESS_OPERATORS(mcr&, uint8_t, raw)
00180         INCREMENT_OPERATORS(mcr, raw)
00181     } mcr;
00182 
00183     //
00184     // Line Status Register (LSR) (read-write) at offset: 0x05
00185     //
00186     union lsr
00187     {
00188         uint8_t raw;
00189 
00190         struct __packed()
00191         {
00192           #if LITTLE_ENDIAN_BITFIELD
00193             unsigned data_ready                   : 1;  // bit 0
00194             unsigned overrun_error                : 1;  // bit 1
00195             unsigned parity_error                 : 1;  // bit 2
00196             unsigned framing_error                : 1;  // bit 3
00197             unsigned break_interrupt              : 1;  // bit 4
00198             unsigned thr_empty                    : 1;  // bit 5
00199             unsigned transmitter_empty            : 1;  // bit 6
00200             unsigned error_in_rcv_fifo            : 1;  // bit 7 (0 on 8250/16450 UARTs)
00201           #elif BIG_ENDIAN_BITFIELD
00202             unsigned error_in_rcv_fifo            : 1;  // bit 7 (0 on 8250/16450 UARTs)
00203             unsigned transmitter_empty            : 1;  // bit 6
00204             unsigned thr_empty                    : 1;  // bit 5
00205             unsigned break_interrupt              : 1;  // bit 4
00206             unsigned framing_error                : 1;  // bit 3
00207             unsigned parity_error                 : 1;  // bit 2
00208             unsigned overrun_error                : 1;  // bit 1
00209             unsigned data_ready                   : 1;  // bit 0
00210           #else
00211             #error unknown bitfield order. fix this.
00212           #endif
00213         };
00214 
00215         ACCESS_FUNCTORS(lsr&, uint8_t, raw)
00216         NUMERIC_ACCESS_OPERATORS(lsr&, uint8_t, raw)
00217         INCREMENT_OPERATORS(lsr, raw)
00218     } lsr;
00219 
00220     //
00221     // Modem Status Register (MSR) (read-write) at offset: 0x06
00222     //
00223     union msr
00224     {
00225         uint8_t raw;
00226 
00227         struct __packed()
00228         {
00229           #if LITTLE_ENDIAN_BITFIELD
00230             unsigned delta_clear_to_send          : 1;  // bit 0
00231             unsigned delta_data_set_ready         : 1;  // bit 1
00232             unsigned trailing_edge_ring_indicator : 1;  // bit 2
00233             unsigned delta_data_carrier_detect    : 1;  // bit 3
00234             unsigned clear_to_send                : 1;  // bit 4
00235             unsigned data_set_ready               : 1;  // bit 5
00236             unsigned ring_indicator               : 1;  // bit 6
00237             unsigned data_carrier_detect          : 1;  // bit 7 (0 on 8250/16450 UARTs)
00238           #elif BIG_ENDIAN_BITFIELD
00239             unsigned data_carrier_detect          : 1;  // bit 7 (0 on 8250/16450 UARTs)
00240             unsigned ring_indicator               : 1;  // bit 6
00241             unsigned data_set_ready               : 1;  // bit 5
00242             unsigned clear_to_send                : 1;  // bit 4
00243             unsigned delta_data_carrier_detect    : 1;  // bit 3
00244             unsigned trailing_edge_ring_indicator : 1;  // bit 2
00245             unsigned delta_data_set_ready         : 1;  // bit 1
00246             unsigned delta_clear_to_send          : 1;  // bit 0
00247           #else
00248             #error unknown bitfield order. fix this.
00249           #endif
00250         };
00251 
00252         ACCESS_FUNCTORS(msr&, uint8_t, raw)
00253         NUMERIC_ACCESS_OPERATORS(msr&, uint8_t, raw)
00254         INCREMENT_OPERATORS(msr, raw)
00255     } msr;
00256 
00257     //
00258     // Scratch Register (SCR) (read-write) at offset: 0x07
00259     //
00260     uint8_t scr;
00261 
00262     //
00263     // get descriptional register names
00264     //
00265     static inline const char *register_name(const uint8_t offset)
00266     {
00267         static const char *names[] = {"RBR/THR", "IER", "IIR/FCR", "LCR",
00268                                       "MCR", "LSR", "MSR", "SCR"};
00269         static_assert(sizeof(names) / sizeof(names[0]) == 8, "names must have 8 elements");
00270         return (offset < 8) ? names[offset] : ">0x07";
00271     }
00272 };
00273 
00274 #endif
00275 
00276 // ***** end of source ***** //
00277