Hello,
I had a situation where CPU 1 accessed the wrong (same as before) physical memory location after it was idle while CPU 0 unmapped the memory page and mapped a different page at the same virtual address afterwards.
When a CPU is idle, its TLB gets marked as 'inactive' in the kernel and the CPU doesn't receive cross-CPU TLB flush requests during this time. It seems there is a TLB flush missing somewhere after CPU 1 leaves the idle thread, to compensate for any missed flush requests during the idle time.
When I added a 'Mem_unit::tlb_flush()' call after 'enable_tlb(cpu)' in 'Kernel_thread::idle_op()' as a test, this problem did not occur anymore.
Christian
Hi,
On Wed Aug 28, 2013 at 20:59:37 +0200, Christian Prochaska wrote:
I had a situation where CPU 1 accessed the wrong (same as before) physical memory location after it was idle while CPU 0 unmapped the memory page and mapped a different page at the same virtual address afterwards.
When a CPU is idle, its TLB gets marked as 'inactive' in the kernel and the CPU doesn't receive cross-CPU TLB flush requests during this time. It seems there is a TLB flush missing somewhere after CPU 1 leaves the idle thread, to compensate for any missed flush requests during the idle time.
When I added a 'Mem_unit::tlb_flush()' call after 'enable_tlb(cpu)' in 'Kernel_thread::idle_op()' as a test, this problem did not occur anymore.
Yes, you're right that's missing there.
Adam
l4-hackers@os.inf.tu-dresden.de
-
Adam Lackorzynski -
Christian Prochaska