Access ARM Data Fault Address Register (System Control Register) in Fiasco.OC

[Stark, Josef]

Hey,

in Fiasco.OC we have a function inside src/kernel/foc/l4/pkg/l4sys/include/thread.h
> L4_INLINE l4_msgtag_t
> l4_thread_ex_regs_ret(l4_cap_idx_t thread, l4_addr_t *ip, l4_addr_t *sp,
>                      l4_umword_t *flags) L4_NOTHROW;
which allows us for a given thread (capability ID) to read its general purpose registers, SP and IP.
Is there a similar function (if not, how could I achieve it) to access the ARM A9 System
control registers or, to be more precise, the Data Fault Address Register (DFAR) [1] of
a thread?
I tried creating a function similar to the above mentioned, but modified the body to do this:
> unsigned int v;
> asm volatile ("mrc p15, 0, %[v], c6, c0, 0" : [v]"=r"(v) :: );
and then write v back to the caller. But this just made the whole system hang.
Any ideas? Thanks in advance!

Best regards,
Josef

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100511_0401_10_en/ric1447333669387.html