Activating the sigma0 thread in the Fiasco kernel

[Paul Boddie]

On Wednesday 7. March 2018 00.27.34 Adam Lackorzynski wrote:
> 
> The asm code sets cp0_status upon exit which includes enabling
> interrupts. Are you sure you're not getting any timer interrupts when
> supposedly running inside sigma0? (Flipping some pixels in the timer
> handler...)

You beat to me a reply! What I was writing just now was that I found the place 
where IE gets set by searching for EXL and (re)discovering the 
Cp0_status::status_eret_to_user_ei method, which provides the appropriate 
value for the status register, incorporating UM (KSU=1), EXL and IE.

This value gets stored in the copy of the register for the thread, and then in 
the assembly language routine containing eret, it gets transferred to the 
actual status register by the instructions in the restore_cp0_status macro.

This contradicts what I wrote earlier because I had tested the status register 
before the restore_cp0_status macro, not realising that it might set IE. At 
that point, only IM2 is set (indicating which interrupt source should be 
enabled). Sorry for the inadvertent misdirection!

So, the conditions for returning to user mode seem to be present together with 
the conditions for subsequent interrupts, and for re-entering the kernel on 
timer interrupts, but somehow the activation of the sigma0 thread doesn't 
succeed.

Currently, I have reason to believe that an exception occurs causing the 
sigma0 thread to terminate, but it's getting late and my debugging efficiency 
is suffering. I think that when the thread terminates, it has the following 
cause register flags set:

ExcCode = 0b01101 (= 11, coprocessor unusable)
IP2 = 1
CE = 0b01

The error exception program counter seems to be given as 0x80210000, which 
doesn't sound consistent with a user mode address, but perhaps the kernel is 
using that register for something else.

So maybe there's some FPU stuff that I haven't managed to eradicate in the 
L4Re code.

Paul