pci_device_base.hpp

#if !defined(__PCI_DEVICE_BASE_HPP__)
#define __PCI_DEVICE_BASE_HPP__

//
// local includes
//
#include "core/machine/devices/device_base.hpp"
#include "pci_config_space.hpp"
#include "pci_device.hpp"
#include "pci_devfn.hpp"

template <typename SpaceT = pci_config_space>
struct pci_device_base : public device_base, public pci_device
{
    typedef SpaceT config_space_type;

    static_assert((is_convertible<config_space_type &, pci_config_header64 &>::conforms),
                  "SpaceT must be a descendant class of pci_config_header64");

    static const bool VERBOSE_ALLOCATION = false;

    static const uint8_t NUM_IOREGIONS = pci_config_header64::NUM_BASE_ADDRESSES + 1;

    static const uint8_t EXPANSION_ROM_SLOT = NUM_IOREGIONS - 1;

  protected:
    config_space_type config_space;

    pci_ioregion ioregions[NUM_IOREGIONS];

  public:
    inline pci_device_base(machine_base &machine, const string &name)
        : device_base(machine, name)
    {}

    //
    // device/device_base: override name & irq_moved:
    //     to disambuigate calls and to write the irq line back to
    //     the PCI configuration space's interrupt line register
    //
    virtual inline const char *name(void) const
    {
        return device_base::name();
    }

    virtual inline void irq_moved(l4_irq_t from, l4_irq_t to)
    {
        device_base::irq_moved(from, to);
        config_space.interrupt_line=to;
    }

    //
    // mmio_handler: override I/O memory (un)map functions
    //     to (un)map PCI I/O memory regions
    //
    virtual l4_hva_t map_mmio_region(int flags, l4_gpa_t base, l4_gpa_t size=1);
    virtual int unmap_mmio_region(l4_gpa_t base, l4_gpa_t size=1);

    //
    // pci_device: override pci_device interface
    //
    virtual int reset(void);

    virtual inline const pci_ioregion *get_ioregion(const uint8_t region_num) const
    {
        return is_valid_ioregion(region_num) ? &ioregions[region_num] : nullptr;
    }

    virtual const search_result search_ioregion(enum pci_ioregion::type type,
                                                l4_gpa_t base, l4_gpa_t size=1) const;

    virtual inline const pci_config_header64 &get_config_space(void) const
    {
        return config_space;
    }

    virtual inline l4_umword_t read_config_space(pci_config_header16::offset_t offset,
                                                 access_size access_size)
    {
        return config_space.read_raw(offset, access_size);
    }

    virtual inline int write_config_space(pci_config_header16::offset_t offset,
                                          l4_umword_t data, access_size access_size);

  protected:
    //
    // device_base: override use_irq & free_irq:
    //     to write the irq line back to the PCI configuration space's interrupt line register
    //
    virtual inline int use_irq(irq_manager::irq_flags use=irq_manager::VIRTUAL,
                               l4_irq_t requested_irq=irq_manager::NO_IRQ,
                               l4_irq_t physical_irq=irq_manager::NO_IRQ,
                               bool verbose=VERBOSE_ALLOCATION)
    {
        const int ret=device_base::use_irq(use, requested_irq, physical_irq, verbose);
        config_space.interrupt_line=(ret >= 0) ? ret : 0;
        config_space.interrupt_pin=(ret >= 0) ? pci_config_header64::PIN_A : pci_config_header64::PIN_NONE;
        return ret;
    }

    virtual inline int free_irq(bool verbose=VERBOSE_ALLOCATION)
    {
        const int ret=device_base::free_irq(verbose);
        config_space.interrupt_line=0;
        config_space.interrupt_pin=pci_config_header64::PIN_NONE;
        return ret;
    }

    //
    // I/O resources management functions
    //
    virtual int use_ioregion(enum pci_ioregion::type type,
                             l4_gpa_t size, l4_hva_t virtual_base=0);

    virtual int use_ioregion(uint8_t region_num, enum pci_ioregion::type type,
                             l4_gpa_t size, l4_hva_t virtual_base=0);

    virtual int ioregion_relocated(uint8_t region_num, l4_gpa_t old_base);

  private:
    //
    // internal write address register: calls ioregion_relocated if necessary
    //
    int write_address_register(pci_config_header16::offset_t offset, l4_gpa_t data,
                               access_size access_size);

  public:
    static inline bool is_valid_ioregion(const uint8_t region_num)
    {
        return region_num < NUM_IOREGIONS;
    }

    static inline uint8_t offset2region_num(const pci_config_header16::offset_t offset)
    {
        return pci_config_header64::is_base_address(offset) ? (offset-0x10) >> 2 : EXPANSION_ROM_SLOT;
    }
};

//
// mmio_handler: I/O memory (un)map functions
//
template <typename SpaceT>
l4_hva_t pci_device_base<SpaceT>::map_mmio_region(int flags, l4_gpa_t base, l4_gpa_t size)
{
    //
    // check constraints
    //
    search_result result=search_ioregion(pci_ioregion::IOMEMORY, base, size);
    assert_logd(L4VMM_DEBUG_PCI, result.is_valid(), "addresses "l4_gpa_fmt"-"l4_gpa_fmt"\n",
                base, base + size - 1);

    pci_ioregion &region=ioregions[result.region_num];
    assert_logd(L4VMM_DEBUG_PCI, region.is_iomemory(), "region_num: %d, type: 0x%08x\n",
                result.region_num, result.region->type);

    //
    // for virtual devices we do not have to map memory here, so simply return
    //     the pointer the device stored for this region
    //
    return result.is_valid() ? region.virtual_base : 0;
}

template <typename SpaceT>
int pci_device_base<SpaceT>::unmap_mmio_region(l4_gpa_t base, l4_gpa_t size)
{
    //
    // check constraints
    //
    search_result result=search_ioregion(pci_ioregion::IOMEMORY, base, size);
    assert_logd(L4VMM_DEBUG_PCI, result.is_valid(), "addresses "l4_gpa_fmt"-"l4_gpa_fmt"\n",
                base, base + size - 1);

    pci_ioregion &region=ioregions[result.region_num];
    assert_logd(L4VMM_DEBUG_PCI, region.is_iomemory(), "region_num: %d, type: 0x%08x\n",
                result.region_num, result.region->type);

    //
    // for virtual devices we do not have to ummap memory here, so simply return success
    //
    return 0;
}

//
// pci_device: override pci_device interface
//
template <typename SpaceT>
int pci_device_base<SpaceT>::reset(void)
{
    for (uint8_t i=0; i < EXPANSION_ROM_SLOT; i++)
        config_space.base_address[i]=ioregions[i].reset();

    config_space.expansion_ROM_address=ioregions[EXPANSION_ROM_SLOT].reset();
    return device_base::reset();
}

template <typename SpaceT>
const pci_device::search_result pci_device_base<SpaceT>::search_ioregion(enum pci_ioregion::type type,
                                                                         l4_gpa_t base, l4_gpa_t size) const
{
    const pci_ioregion *region=ioregions;
    for (int i=0; i < NUM_IOREGIONS; i++, region++)
        if (region->is_used() && region->is(type) && region->contains(base, size))
            return search_result(region, i);

    return search_result();
}

template <typename SpaceT>
int pci_device_base<SpaceT>::write_config_space(pci_config_header16::offset_t offset,
                                                l4_umword_t data, access_size access_size)
{
    // unconditionally return 0, if this offset (register) was handled
    if (config_space.is_readonly(offset))
        return 0;

    if (config_space.is_status(offset) && (access_size == access_size::WORD)) {
        config_space.status&=~le2cpu<uint16_t>(data);
        return 0;
    }

    if (config_space.is_address(offset) && (access_size == access_size::DWORD)) {
        write_address_register(offset, data, access_size);
        return 0;
    }

    if (config_space.is_interrupt_line(offset) && (access_size == access_size::BYTE)) {
        config_space.interrupt_line=data;
        return 0;
    }

    if (config_space.is_bist(offset) && (access_size == access_size::BYTE))
        // reset start bit and set completion code to 0 (OK)
        if (data & 0x40) config_space.bist&=0x80;

    // no offset (register) that can be handled generically
    return -L4_ENOTSUPP;
}

//
// I/O resources management functions
//
template <typename SpaceT>
int pci_device_base<SpaceT>::use_ioregion(enum pci_ioregion::type type,
                                          l4_gpa_t size, l4_hva_t virtual_base)
{
    if (type == pci_ioregion::ROM)
        return use_ioregion(EXPANSION_ROM_SLOT, type, size, virtual_base);

    // search for free slot to use. last entry is expansion ROM address
    for (uint8_t i=0; i < EXPANSION_ROM_SLOT; i++)
        if (!ioregions[i].is_used()) return use_ioregion(i, type, size, virtual_base);

    log::error("%s:\n  too many I/O regions, only %u regions available\n",
               name(), NUM_IOREGIONS);
    return -L4_ENOTAVAIL;
}

template <typename SpaceT>
int pci_device_base<SpaceT>::use_ioregion(uint8_t region_num, enum pci_ioregion::type type,
                                          l4_gpa_t size, l4_hva_t virtual_base)
{
    if (region_num >= NUM_IOREGIONS) {
        log::error("%s:\n  invalid I/O region #%u, only 0-%u available\n",
                   name(), region_num, NUM_IOREGIONS-1);
        return -L4_EINVAL;
    }

    if ((type == pci_ioregion::ROM) && (region_num != EXPANSION_ROM_SLOT)) {
        log::error("%s:\n  expansion ROM must be I/O region #%u\n", name(), EXPANSION_ROM_SLOT);
        return -L4_EINVAL;
    }

    if ((1ul << bitops::highest_set_bit(size)) != size) {
        log::error("%s:\n  I/O region size "l4_gpa_fmt" must be a power of 2\n", name(), size);
        return -L4_EINVAL;
    }

    pci_ioregion &region=ioregions[region_num];
    if (region.is_used()) {
        log::error("%s:\n  I/O region #%u is already used\n", name(), region_num);
        return -L4_EBUSY;
    }

    // base is set by client operating system
    region(type, 0, size, virtual_base);

    if (region_num == EXPANSION_ROM_SLOT) config_space.expansion_ROM_address=region;
    else config_space.base_address[region_num]=region;
    return region_num;
}

//
// simple implementation which registers itself as I/O space or MMIO handler
//     override if you want different handlers for different I/O regions
//
template <typename SpaceT>
int pci_device_base<SpaceT>::ioregion_relocated(uint8_t region_num, l4_gpa_t old_base)
{
    const pci_ioregion &region=ioregions[region_num];

    //
    // I/O space regions
    //
    if (region.is_iospace()) {
        log::info("%s:\n  region #%u: "l4_port_fmt" -> ",
                  name(), region_num, static_cast<l4_port_t>(old_base));
        region.print_short("", "\n");

        // use VERBOSE_ALLOCATION ?
        if ((old_base != 0) && iospace_manager::is_valid_ioport(old_base))
            free_iospace(old_base, region.size, true);
        if ((region.base != 0) && iospace_manager::is_valid_ioport(region.base))
            use_iospace(region.base, region.size, true);
    }

    //
    // memory regions (including expansion ROM)
    //
    else if (region.is_iomemory()) {
        log::info("%s:\n  region #%u: "l4_gpa_fmt" -> ", name(), region_num, old_base);
        region.print_short("", "\n");

        // use VERBOSE_ALLOCATION ?
        if (old_base != 0) free_iomemory(old_base, region.size, true);
        if (region.base != 0) use_iomemory(region.base, region.size, true);
    }

    return 0;
}

//
// internal write address register: calls ioregion_relocated if necessary
//
template <typename SpaceT>
int pci_device_base<SpaceT>::write_address_register(pci_config_header16::offset_t offset,
                                                    l4_gpa_t data, access_size access_size)
{
    if (access_size != access_size::DWORD) return -L4_ENOTSUPP;

    const uint8_t region_num=offset2region_num(offset);
    pci_ioregion &region=ioregions[region_num];
    if (!region.is_used()) return -L4_EUNUSED;

    //
    // shortcut to omit unnecessary resource relocations:
    //     don't locate the region when the client tries to get its size
    //     (and if it hasn't been located before). only write the PCI configuration space value.
    //
    if (!region.is_located() && (data == ~0u)) {
        config_space.write(offset, region.template size2bar<uint32_t>());
        return 0;
    }

    //
    // update I/O region & the PCI configuration space value
    //
    const l4_gpa_t old_base=region.base;
    region.base=le2cpu<uint32_t>(data) & region.size_mask();
    config_space.write(offset, region.template base2bar<uint32_t>());

    return (region.base != old_base) ? ioregion_relocated(region_num, old_base) : 0;
}

#endif

// ***** end of source ***** //