piix_ide.hpp

#if !defined(__PIIX3_IDE_HPP__)
#define __PIIX3_IDE_HPP__

//
// local includes
//
#include "core/protocols/ata/ata_bm_block.hpp"
#include "core/protocols/ata/ata_channel.hpp"
#include "piix_ide_config_space.hpp"

struct piix_ide : public pci_device_base<piix_ide_config_space>
{
    static const bool VERBOSE_ALLOCATION = false;

  protected:
    typedef pci_device_base<piix_ide_config_space> super_type;

    //
    // default (compat mode) I/O space bases, otherwise located via address registers 0-3
    //
    static const struct compat_resource
    {
        l4_port_t command_base, control_base;
        l4_irq_t irq;
    } compat_resources[];

    //
    // chip descriptions. describe the chips that can be emulated.
    //
    static const struct chip_descriptor
    {
        const char *name;
        uint16_t deviceID;
        const char *device_name;
        bool native_supported;

        static const chip_descriptor *get(const string &name);
    } chip_descriptors[];

    enum ata_state_constants
    {
        DECODE_ENABLED        = 0x01,   // the channel decodes I/O space accesses
        COMMAND_REGISTERED    = 0x02,   // ... and the command block handler is registered
        CONTROL_REGISTERED    = 0x04,   // ... and the control block handler is registered
        IRQ_REGISTERED        = 0x08,   // the channel is assigned an IRQ
        NATIVE_MODE_SUPPORTED = 0x10,   // the channel supports native PCI mode (otherwise compat mode)
        NATIVE_MODE_ENABLED   = 0x20,   // the channel is in native PCI mode (otherwise compat mode)

        // masks
        ALL_MASK              = DECODE_ENABLED | COMMAND_REGISTERED | CONTROL_REGISTERED |
                                IRQ_REGISTERED | NATIVE_MODE_SUPPORTED | NATIVE_MODE_ENABLED
    };

    typedef bitmask<uint_value_t<ALL_MASK>::least> ata_state;
    static_assert(integer_traits<ata_state::word_type>::const_max >= ALL_MASK,
                  "ata_state's max value is too small");

    //
    // the states the channels are operating in
    //
    ata_state ata_states[2];

    //
    // the 2 channels itself
    //
    ata_channel ata0, ata1;

    //
    // BM-DMA register block located via the PCI configuration space's base address register #4
    //
    ata_bm_block bm_block;

  public:
    piix_ide(machine_base &machine, ata_drive *drives[4],
             const chip_descriptor *chip=nullptr, bool native_enabled=true);

    //
    // iospace_handler: override I/O space access handlers
    //
    virtual uint32_t read_ioport(l4_port_t port, access_size access_size);
    virtual int write_ioport(l4_port_t port, uint32_t data, access_size access_size);

    //
    // pci_device: override reset & PCI configuration space write handler
    //
    virtual int reset(void);
    virtual int write_config_space(pci_config_header16::offset_t offset,
                                   l4_umword_t data, access_size access_size);

    //
    // pci_device_base: override ioregion_relocated
    //     to suppress immediate handler registration when the register is written,
    //     which would only be necessary, if the channel is in native mode.
    //
    virtual int ioregion_relocated(uint8_t region_num, l4_gpa_t old_base);

  protected:
    //
    // channel management functions
    //
    inline ata_channel &get_channel(const uint8_t channel_ix)
    {
        return (channel_ix & 0x01) ? ata1 : ata0;
    }

    int enable_ports(uint8_t channel_ix, bool enable=true, bool verbose=VERBOSE_ALLOCATION,
                     l4_port_t command_base=0, l4_port_t control_base=0);
    int enable_irqs(uint8_t channel_ix, bool enable=true, bool verbose=VERBOSE_ALLOCATION);
    int enable_channel(uint8_t channel_ix, bool enable=true, bool verbose=VERBOSE_ALLOCATION);
    int enable_native_mode(uint8_t channel_ix, bool enable=true, bool verbose=VERBOSE_ALLOCATION);

    void start_stop_DMA(uint8_t channel_ix);

  public:
    static pci_device *create(machine_base &machine, config_node &device_node);
};

#endif

// ***** end of source ***** //