Lapic Class Reference

Lapic model. More...

Inheritance diagram for Lapic:

Public Member Functions
bool	receive (MessageMem &msg)
	Receive MMIO access.
bool	receive (MessageMemRegion &msg)
	Receive MMIO map request.
bool	receive (MessageTimeout &msg)
	Timeout for the APIC timer.
bool	receive (MessageApic &msg)
	Receive an IPI.
bool	receive (LapicEvent &msg)
	Receive INTA cycle or RESET from the CPU.
bool	receive (CpuMessage &msg)
	Receive RDMSR and WRMSR messages.
bool	receive (MessageLegacy &msg)
	Legacy pins.
void	discovery ()
	Lapic (Motherboard &mb, VCpu *vcpu, unsigned initial_apic_id, unsigned timer)
Public Member Functions inherited from StaticReceiver< Lapic >
	StaticReceiver ()
Public Member Functions inherited from Device
void	debug_dump ()
	Device (const char *debug_name)

Public Attributes
Motherboard &	_mb

Private Types
enum	{   MAX_FREQ = 200000000, LVT_MASK_BIT = 16, OFS_ISR = 0, OFS_TMR = 256,   OFS_IRR = 512, LVT_BASE = _TIMER_offset, NUM_LVT = 6, APIC_ADDR = 0xfee00000 }

Private Member Functions
bool	sw_disabled ()
bool	hw_disabled ()
bool	x2apic_mode ()
unsigned	x2apic_ldr ()
void	init ()
	Handle an INIT signal.
void	reset ()
	Reset the APIC to some default state.
bool	set_base_msr (unsigned long long value)
	Update the APIC base MSR.
unsigned	get_ccr (timevalue now)
	Checks whether a timeout should trigger and returns the current counter value.
void	update_timer (timevalue now)
	Reprogram a new host timer.
bool	send_ipi (unsigned icr, unsigned dst)
	We send an IPI.
unsigned	get_highest_bit (unsigned bit_offset)
	Scan for the highest bit in the ISR or IRR.
unsigned	processor_prio ()
	Calc the PPR.
unsigned	prioritize_irq ()
	Check whether there is an EXTINT in the LVTs or an IRQ above the processor prio to inject.
void	update_irqs ()
	Send upstream to the CPU that we have an IRQ.
bool	set_error (unsigned bit)
	Indicate an error and trigger the error LVT.
void	accept_vector (unsigned char vector, bool level, bool value)
	Accept a fixed vector in the IRR.
void	broadcast_eoi (unsigned vector)
	Broadcast an EOI on the bus if it is level triggered.
bool	register_read (unsigned offset, unsigned &value)
bool	register_write (unsigned offset, unsigned value, bool strict)
bool	trigger_lvt (unsigned num)
	Trigger an LVT entry.
bool	accept_message (MessageApic &msg)
	Check whether we should accept the message.

Private Attributes
VCpu *	_vcpu
unsigned	_initial_apic_id
unsigned	_timer
unsigned	_timer_clock_shift
unsigned	_timer_dcr_shift
timevalue	_timer_start
unsigned long long	_msr
unsigned	_vector [8 *3]
unsigned	_esr_shadow
unsigned	_isrv
bool	_lvtds [NUM_LVT]
bool	_rirr [NUM_LVT]
unsigned	_lowest_rr

Additional Inherited Members
Static Public Member Functions inherited from DiscoveryHelper< Lapic >
static bool	discover (Device *o, MessageDiscovery &msg)
Static Public Member Functions inherited from StaticReceiver< Lapic >
static bool	receive_static (Device *o, M &msg)
Protected Member Functions inherited from DiscoveryHelper< Lapic >
bool	discovery_write_st (const char *resource, unsigned offset, const void *value, unsigned count)
bool	discovery_write_dw (const char *resource, unsigned offset, unsigned value, unsigned count=4)
	Write a dword or less than it.
bool	discovery_read_dw (const char *resource, unsigned offset, unsigned &value)
	Read a dword.
unsigned	discovery_length (const char *resource, unsigned minlen)
	Return the length of an ACPI table or minlen if it is smaller.

Detailed Description

Lapic model.

State: testing Features: MEM, MSR, MSR-base and CPUID, LVT, LINT0/1, EOI, prioritize IRQ, error, RemoteEOI, timer, IPI, lowest prio, reset, x2apic mode, BIOS ACPI tables Missing: focus checking, CR8/TPR setting Difference: no interrupt polarity, lowest prio is round-robin Documentation: Intel SDM Volume 3a Chapter 10 253668-033.

Member Enumeration Documentation

anonymous enum

private

Enumerator:

MAX_FREQ
LVT_MASK_BIT
OFS_ISR
OFS_TMR
OFS_IRR
LVT_BASE
NUM_LVT
APIC_ADDR

Constructor & Destructor Documentation

Lapic::Lapic ( Motherboard &  mb, VCpu *  vcpu, unsigned  initial_apic_id, unsigned  timer  )

inline

Member Function Documentation

bool Lapic::accept_message ( MessageApic &  msg )

inlineprivate

Check whether we should accept the message.

void Lapic::accept_vector ( unsigned char  vector, bool  level, bool  value  )

inlineprivate

Accept a fixed vector in the IRR.

void Lapic::broadcast_eoi ( unsigned  vector )

inlineprivate

Broadcast an EOI on the bus if it is level triggered.

void Lapic::discovery ( )

inline

unsigned Lapic::get_ccr ( timevalue  now )

inlineprivate

Checks whether a timeout should trigger and returns the current counter value.

unsigned Lapic::get_highest_bit ( unsigned  bit_offset )

inlineprivate

Scan for the highest bit in the ISR or IRR.

bool Lapic::hw_disabled ( )

inlineprivate

void Lapic::init ( )

inlineprivate

Handle an INIT signal.

unsigned Lapic::prioritize_irq ( )

inlineprivate

Check whether there is an EXTINT in the LVTs or an IRQ above the processor prio to inject.

unsigned Lapic::processor_prio ( )

inlineprivate

Calc the PPR.

bool Lapic::receive ( MessageMem &  msg )

inline

Receive MMIO access.

bool Lapic::receive ( MessageMemRegion &  msg )

inline

Receive MMIO map request.

We return true without setting msg.ptr and thus nobody else can claim this region.

bool Lapic::receive ( MessageTimeout &  msg )

inline

Timeout for the APIC timer.

bool Lapic::receive ( MessageApic &  msg )

inline

Receive an IPI.

bool Lapic::receive ( LapicEvent &  msg )

inline

Receive INTA cycle or RESET from the CPU.

bool Lapic::receive ( CpuMessage &  msg )

inline

Receive RDMSR and WRMSR messages.

bool Lapic::receive ( MessageLegacy &  msg )

inline

Legacy pins.

bool Lapic::register_read ( unsigned  offset, unsigned &  value  )

inlineprivate

bool Lapic::register_write ( unsigned  offset, unsigned  value, bool  strict  )

inlineprivate

void Lapic::reset ( )

inlineprivate

Reset the APIC to some default state.

bool Lapic::send_ipi ( unsigned  icr, unsigned  dst  )

inlineprivate

We send an IPI.

This is a strange thing in the manual: lowest priority with a broadcast shorthand is invalid. But what about physical destination mode with dst=0xff?

bool Lapic::set_base_msr ( unsigned long long  value )

inlineprivate

Update the APIC base MSR.

bool Lapic::set_error ( unsigned  bit )

inlineprivate

Indicate an error and trigger the error LVT.

Make sure we do not loop, if the ERROR LVT has also an invalid vector programmed.

bool Lapic::sw_disabled ( )

inlineprivate

bool Lapic::trigger_lvt ( unsigned  num )

inlineprivate

Trigger an LVT entry.

It is not defined how invalid Delivery Modes are handled. We simply drop SIPI, RRD and LOWEST here.

void Lapic::update_irqs ( )

inlineprivate

Send upstream to the CPU that we have an IRQ.

void Lapic::update_timer ( timevalue  now )

inlineprivate

Reprogram a new host timer.

unsigned Lapic::x2apic_ldr ( )

inlineprivate

bool Lapic::x2apic_mode ( )

inlineprivate

Member Data Documentation

unsigned Lapic::_esr_shadow

private

unsigned Lapic::_initial_apic_id

private

unsigned Lapic::_isrv

private

unsigned Lapic::_lowest_rr

private

bool Lapic::_lvtds[NUM_LVT]

private

Motherboard& Lapic::_mb

unsigned long long Lapic::_msr

private

bool Lapic::_rirr[NUM_LVT]

private

unsigned Lapic::_timer

private

unsigned Lapic::_timer_clock_shift

private

unsigned Lapic::_timer_dcr_shift

private

timevalue Lapic::_timer_start

private

VCpu* Lapic::_vcpu

private

unsigned Lapic::_vector[8 *3]

private

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The documentation for this class was generated from the following file:

• vancouver/model/lapic.cc