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"Adam 'WeirdArms' Wiggins" <awiggins(a)cse.unsw.edu.au> writes:
> What TID does the kernel use for its ipc to Sigma0 to request
> memory mapping for kernel usage.
L4/x86 uses task 1, local thread 0, for communication with Sigma0.
The Fiasco kernel doesn't do any IPC operations on behalf of itself --
so no thread id here.
Michael
--
hohmuth(a)innocent.com, hohmuth(a)sax.de
http://www.sax.de/~hohmuth/
Robert Kaiser <rob(a)sysgo.de> writes:
> I was aware that the bookkeeping would have to be in the kernel, otherwise
> flush couldn't work as described in the manual. Only, how does it work ?
>
> Theoretically, each task could map each of it's pages to up to 2047 other
> tasks. So, the kernel would need to maintain ~2K entries per mapped page
> and task. This can't be! The only explanation I can think of right now
> is that the kernel allocates room for entries …
[View More]dynamically, assuming that
> the actual number of required entries will always be far less than
> the theoretical limit. But that would mean you can break the system
> simply by doing a big enough number of mappings.
Each mapping of a physical page from virtual address VA1 in a task T1
to VA2 in T2 is kept track of using a kernel data structure called
``mapping entry.'' This data structure is allocated dynamically, but
from a fixed-size pool (where the size can be specified at compile
time or boot time).
It's true that you can break the system by establishing an excessive
number of mappings. There are several ways to deal with that, but I
don't think any of them has been implemented in the freely-available
research kernels; one way is detailed in Jochen Liedtke et al.'s paper
``Preventing Denial-of-Service Attacks on a µ-Kernel for WebOSes''
which is available from
<URL:http://os.inf.tu-dresden.de/papers_ps/jochen/Denhot.ps>.
> On Mon, 22 Feb 1999, Volkmar Uhlig wrote:
> > In the current L4-implementation of Jochen Liedtke, one mapping entry is 16
> > Bytes.The Alpha implementation (done by me) needs 32 Bytes per entry (64
> > bit address space - and a lot of trix). The Fiasco kernel does not use
> > lists. They need about 4 Bytes per entry + an some overhead per frame (I
> > left bevore it was finished)
>
> I am getting the distinct feeling that I am missing something
> very simple :-(. So, at the risk of looking like a complete fool:
> How do you keep track of up to 2K tasks in a 16 Byte entry ?
The 16-bytes structure is what I described as a ``mapping entry''
above. Mapping entries belonging to one physical page are linked to
each other in a binary-tree structure using pointers.
Michael
--
hohmuth(a)innocent.com, hohmuth(a)sax.de
http://www.sax.de/~hohmuth/
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vuhlig(a)us.ibm.com writes:
> The idea is, that the kernel can revoke pages from sigma 0, what is not
> implemented yet. [...]
I don't think it is a part of the Sigma0 specification that Sigma0
should be able to handle the case where the kernel revokes mappings of
pages mapped into Sigma0. Instead, Sigma0 is pretty safe to assume
that it magically owns---and has access to---all physically-
addressable memory (maybe with the exception of the kernel-private
code and data sections; the …
[View More]experts are still out on this one).
Michael
--
hohmuth(a)innocent.com, hohmuth(a)inf.tu-dresden.de
http://home.pages.de/~hohmuth/
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I wrote:
> The resource manager Rmgr (which is normally used to startup L4/x86
> and Fiasco) handles the nitty-gritty details of telling the kernel
> where it should find its Sigma0 server.
In order to avoid any confusion: In a typical booting scenario on the
x86, the Rmgr bootstrappig code runs even before the L4 or Fiasco
kernel has been started. It is invoked directly by the boot loader
and handles all initializations to be done before the kernel starts
up: It finds the raw ELF …
[View More]binaries for the kernel and Sigma0 which the
boot-loader has dropped in memory, interpretes them (i.e., moves them
to their load addresses), configures the kernel (e.g., tells it the
location of Sigma0 and Rmgr task entry points), and starts it.
For more information, please read the Rmgr manpage at
<URL:http://os.inf.tu-dresden.de/L4/l4libman/rmgr.html>.
Michael
--
hohmuth(a)innocent.com, hohmuth(a)sax.de
http://www.sax.de/~hohmuth/
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Hi all,
I have a question regarding mapping in L4:
I read in the L4 reference manual that Sigma0 maps each page
only once. It does allow multiple mappings of a page to the
same address space (i.e. task), but it does not allow multiple
mappings to different tasks.
Is this a specific feature of Sigma0 or is this true of all
pagers ?
I'm asking because I wonder how the fpage_unmap operation
works: If a task is allowed to map a page to an unlimited
number of different tasks (i.e. 2047 as there …
[View More]are up to 2048
tasks), then the bookkeeping involved in implementing fpage_unmap
would require that a pager would theoretically need to keep
track of up to 2047 tasks per page in order to allow fpage_unmap
to revoke all mappings of a particular page.
That looks like a tremendous overhead, so there must either be
some limit to the number of mappings or there is something else
I'm missing.
Could someone please enlighten me about this ?
Thanks in advance
Rob
----------------------------------------------------------------
Robert Kaiser email: rkaiser(a)sysgo.de
SYSGO RTS GmbH
Carl-Zeiss-Str. 41 phone: (49) 6131 9138-80
D-55129 Mainz / Germany fax: (49) 6131 9138-10
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"Adam 'WeirdArms' Wiggins" <awiggins(a)cse.unsw.edu.au> writes:
> A related question here. Is there any particular reason/need for
> sigma zero to be a once off pager? Why not have an inteligent resource
> manager for sigma zero?
In L4/x86 and Fiasco, this is easily possible. Sigma0 runs on user
level and can be substituted at boot time with any program you like.
The resource manager Rmgr (which is normally used to startup L4/x86
and Fiasco) handles the nitty-gritty details …
[View More]of telling the kernel
where it should find its Sigma0 server.
Michael
--
hohmuth(a)innocent.com, hohmuth(a)sax.de
http://www.sax.de/~hohmuth/
[View Less]
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Hi Robert,
the 5 mappings are on average (and configurable!). They are not assigned to
one particular frame. I used the term frame in the context of available
physical memory. you need some additional mapping entries for devices (like
video frame buffer). The kernel must keep track of the mappings, because
otherwise the pager can not revoke a page from an address space, where the
page was indirectly mapped to. (e.g. A=pager mapps to B and maps to C, D,
and E. Hereby, A is only aware of the …
[View More]mapping to B.) But the kernel concept
allows to map any available/mapped memory from one address space to
another.
Volkmar
Robert Kaiser <rob(a)sysgo.de> on 02/22/99 11:43:16 AM
Please respond to Robert Kaiser <rob(a)sysgo.de>
To: Volkmar Uhlig/Watson/IBM
cc:
Subject: RE: L4 Mapping question
Hi Volkmar
Thanks again for your response!
On Mon, 22 Feb 1999 vuhlig(a)us.ibm.com wrote:
> there is one mapping entry per associated page per address space. that
> means, if you map a page to 2 address spaces you need 2 mappings. The
> current L4 version allocates the mappings statically (currently 5 entries
> per frame, but this is configurable at startup time).
I seem to have a little difficulty with the term "frame". It may have
to do with the fact that I don't have much of an Intel background (I'm
developing mostly for MIPS machines). Does it mean something like
"physical page" ?
If so, that would mean that there is a hard (though configurable) limit
of five address spaces that can share any given page. Is that correct ?
> The idea is, that the kernel can revoke pages from sigma 0, what is not
> implemented yet. I don't see the case, where you want to map a lot of
pages
> into all address spaces.
The case I had in mind is shared memory between user tasks running
on top of a -say- L4Linux server (and possibly being unaware that
they are in a microkernel environment).
I would not like the microkernel to impose a limit on the number of
tasks that can share a given piece of memory.
> Furthermore is your calculation not right. You can
> map a page to multiple address spaces multiple times (at different
virtual
> addresses) - so there is no limit of needed mapping-entries per page.
Oops, I hadn't thought of that!
Would it be such a bad idea to move the bookkeeping for fpage_unmap
out of the microkernel altogether? I mean, the pager has to do some
bookkeeping anyway (like Sigma0 marks all pages once it maps them
so it can refuse multiple mapping attempts). So, if the fpage_unmap
syscall would just unmap a given fpage for a *single*, given address
space and the pager would be responsible for making one fpage_unmap
call for each task it has previously mapped the fpage to, then all
bookkeeping would be in one place (i.e. the pager). This would
simplify the microkernel, reduce it's memory footprint and leave
the implementation details up to the user-space pager, which seems
to me like the "microkernel way" of doing things.
Of course, this would result in more system calls being made (thus
more overhead), but I guess that in the usual cases (such as up to
five tasks sharing a page) this should be negligible.
I suppose there must be some other good reason why it wasn't done
this way...
Thanks again
Rob
----------------------------------------------------------------
Robert Kaiser email: rkaiser(a)sysgo.de
SYSGO RTS GmbH
Carl-Zeiss-Str. 41 phone: (49) 6131 9138-80
D-55129 Mainz / Germany fax: (49) 6131 9138-10
[View Less]