Hi all,
I would like to try Fiasco/L4Re for a Mixed-Critical Xilinx UltraScale+
FPGA-MPSoC (the hardware accelerators on the FPGA should be
virtualized/isolated for mixed-critical applications) Is there somewhere
an example (or at least starting point) of an ARM Trustzone
configuration of a Normal World VM and Secure World VM (with UVMM/Fiasco
as hypervisor that also takes care of the ARM Trustzone configuration)?
Best regards
Micha
