l4-hackers September 2011

l4-hackers@os.inf.tu-dresden.de

11 participants
17 discussions

l4sigma0_map_iomem Allowed Addresses
by Wesley Miaw 18 Oct '11

18 Oct '11

I'm having some trouble understanding the acceptable values usable in a call to l4sigma0_map_iomem. It looks like the way for me to request a map from an available physical address block to a virtual memory address that can be used by the program. Perhaps I am lacking a more fundamental understanding of the ARM memory model. But what addresses should be allowed? My Verstaile Express board has 1GB RAM starting at physical address 0x60000000 but I can't use this address. I immediately get an error. I also tried starting at 0x80000000. (The L4 Bootloader seems to be using memory at 0x60000000 for its own purposes anyway.) Error: Cannot map physical memory: (-2147451404) No fpage received If I try to get size 0x04000000 from address 0x08000000 it works fine. I am going off the memory map of the CoreTile A9x4. http://infocenter.arm.com/help/topic/com.arm.doc.dui0448e/CIAGFCHA.html#BBA… The CoreTile A9x4 uses the Versatile Express Motherboard uATX's Legacy memory map. http://infocenter.arm.com/help/topic/com.arm.doc.dui0447e/ch04s02s01.html#C… Thanks, -- Wesley Miaw wesley(a)wesman.net

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Is there a way to build a non-PIC shared library with l4env?
by Valery V. Sedletski 17 Oct '11

17 Oct '11

Hi, I am trying to establish a shared arena for loading DLL's, i.e. a shared memory region, in which DLL's are loaded at the same address in each address space. I also need some ELF shared library loaded at fixed address, so I could call routines in .so from these DLL's (yes, a mixed case: LX format DLL's calling an ELF shared object, this shared object is a client library for some servers, and I want to call their API's from DLL's). So, I intend to load a shared oblect at fixed address to be the same in different address spaces. But the l4env build system seems to produce PIC shared objects only, and no suitable example. Is there any way to compile a non-PIC shared object with l4env build system? I also hope the 'loader' server will load the shared library at pre-compiled address. Maybe, also the PIC ones could be loaded at desired address (I know that, at least, libloader.s.so is loaded at fixed address, but maybe, this is a single hardcoded case) Thanks in advance, valery

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l4 task map in different factory.
by Chen Tian 02 Oct '11

02 Oct '11

Hello, If I create a new factory and using it to create a new task, can I map capability slots in this new task to some slots in a task that is created by an old (different) factory? Thanks. Chen

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L4 courses
by Slex Sangiuliano 23 Sep '11

23 Sep '11

Morning, i'm searching some university courses that use L4. Searching on the net i found a document that talks of a university with a O.S. course with the target to build a small operating system based on l4 at the end of the course. Unfortunatly i haven't found slides and the university. Do you know some univeristy that uses l4 for the O.S. course? Thanks and sorry for the stupid request. Slex

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VM API for TZ Decl != Impl
by Wesley Miaw 17 Sep '11

17 Sep '11

It looks like the definitions for l4_vm_run and l4_vm_run_u in vm.h are incorrect? The implementation signatures look like what they are supposed to be, as called from L4::Vm::run(...) in the 'vm' file in the same directory. -- Wesley Miaw wesley(a)wesman.net

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clntsrv example capabilities
by Wesley Miaw 17 Sep '11

17 Sep '11

Hi, I'm still trying to fully understand capabilities, and I guess maybe what I need to do is create a new capability of some sort, but I thought asking might help me understand better. Basically, I am trying to build an example like the clntsrv example, and the server.cc attempts to register itself. If that fails, it prints out an error message saying "Readonly namespace?". I guess this is because the namespace is still 'rom'. I tried understanding the contents of the various .cfg files but I'm afraid I'm still confused. Thanks, -- Wesley Miaw wesley(a)wesman.net

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pthread issue on ARM
by Ivan Loskutov 16 Sep '11

16 Sep '11

Hello, Hackers! I trying to porting a library from Linux to L4Re and I got a issue with libpthread on ARM device (beagleboard clone). If I create a detached thread use pthread_detach() or pthread attributes then error is occured. Error does not occur on x86, tested in qemu. I wrote a simple programm for test. Is problem in L4Re? Or should I make any steps before use pthread? Thank you! Code: #include <stdio.h> #include <string.h> #include <pthread.h> void *thread(void* arg) { int res; int num = (int)arg; printf("Start thread %d\n", num); res = pthread_detach(pthread_self()); printf("Detach thread %d (%d)\n", num, res); usleep(5000*num); printf("End thread %d\n", num); return 0; } int main(int argc, char* argv[]) { pthread_t t1, t2; printf("Test pthread\n"); while(1) { printf("new loop...\n"); pthread_create(&t1, NULL, thread, (void*)1); pthread_create(&t2, NULL, thread, (void*)2); usleep(100000); } return 0; } Log: Starting kernel ... L4 Bootstrapper Build: #101 Срд Сен 14 16:32:30 MSD 2011, 4.4.1 Scanning up to 128 MB RAM Memory size is 128MB (80000000 - 88000000) RAM: 0000000080000000 - 0000000087ffffff: 131072kB Total RAM: 128MB mod04: 810c5000-810e7ec0: pthread_test mod03: 810aa000-810c439c: l4re mod02: 8106f000-810a9b50: moe mod01: 81065000-8106e70c: sigma0 mod00: 81015000-81064f74: fiasco Moving 5 modules to 81100000 with offset eb000 moving module 05 { 810c5000-810e7ec0 } -> { 811b0000-811d2ec0 } moving module 04 { 810aa000-810c439c } -> { 81195000-811af39c } moving module 03 { 8106f000-810a9b50 } -> { 8115a000-81194b50 } moving module 02 { 81065000-8106e70c } -> { 81150000-8115970c } moving module 01 { 81015000-81064f74 } -> { 81100000-8114ff74 } Scanning fiasco Scanning sigma0 Scanning moe --init=rom/pthread_test Relocated mbi to [0x8100f000-0x8100f0e4] Loading fiasco Loading sigma0 Loading moe find kernel info page... found kernel info page at 0x80002000 Regions of list regions [ 80001000, 800019ff] { a00} Kern fiasco [ 80002000, 80061fff] { 60000} Kern fiasco [ 80090000, 800969bf] { 69c0} Sigma0 sigma0 [ 80098000, 8009e17b] { 617c} Sigma0 sigma0 [ 80140000, 8017618b] { 3618c} Root moe [ 80178000, 8018ed0f] { 16d10} Root moe [ 81000000, 810143eb] { 143ec} Boot bootstrap [ 8100f000, 8100f1e1] { 1e2} Root Multiboot info [ 81195000, 811d2ebf] { 3dec0} Root Modules Memory API Version: (87) experimental Sigma0 config ip:800900e0 sp:81013704 Roottask config ip:801401c0 sp:00000000 Starting kernel fiasco at 80001000 Hello from Startup::stage2 Initialize page table Vmem_alloc::init() Cache config: ON ID_PFR0: 00001031 ID_PFR1: 00000011 ID_DFR0: 00010400 ID_AFR0: 00000000 ID_MMFR0: 31100003 ID_MMFR1: 20000000 ID_MMFR2: 01202000 ID_MMFR3: 00000011 FPU0: Arch: VFPv3(3), Part: VFPv3(30), r: 1, v: c, i: 41, t: hard, p: dbl/sngl Welcome to Fiasco.OC (arm)! L4/Fiasco.OC arm microkernel (C) 1998-2011 TU Dresden Rev: rUNKNOWN compiled with gcc 4.4.1 for Beagleboard [] Build: #1 Чтв Сен 8 11:49:39 MSD 2011 Calibrating timer loop... done. SIGMA0: Hello! KIP @ 80002000 allocated 4KB for maintenance structures SIGMA0: Dump of all resource maps RAM:------------------------ [0:80000000;80000fff] [0:80062000;8008ffff] [0:80097000;80097fff] [0:8009f000;8013ffff] [4:80140000;80176fff] [0:80177000;80177fff] [4:80178000;8018efff] [0:8018f000;8100efff] [4:8100f000;8100ffff] [0:81010000;81194fff] [4:81195000;811d2fff] [0:811d3000;86ffffff] IOMEM:---------------------- [0:0;7fffffff] [0:88000000;ffffffff] MOE: Hello world MOE: found 113680 KByte free memory MOE: found RAM from 80000000 to 87000000 MOE: allocated 112 KByte for the page array @0x80062000 MOE: virtual user address space [0-bfffffff] MOE: rom name space cap -> [C:501000] BOOTFS: [81195000-811af39c] [C:503000] l4re BOOTFS: [811b0000-811d2ec0] [C:504000] pthread_test MOE: cmdline: moe --init=rom/pthread_test MOE: Starting: rom/pthread_test MOE: loading 'rom/pthread_test' Test pthread new loop... Start thread 1 Detach thread 1 (0) Start thread 2 Detach thread 2 (0) End thread 1 L4Re[rm]: unhandled read page fault @300d3c pc=1003b54 L4Re: unhandled exception: pc=0x1003b54 End thread 2 new loop... modules.list: modaddr 0x01100000 entry pthread_test roottask moe --init=rom/pthread_test module l4re module pthread_test

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L4Re/L4Android specify RAM size on Beagleboard
by giowck 15 Sep '11

15 Sep '11

Hi, when running L4Linux/L4Android on the Beagleboard (rev. C4), only 128MB of 256MB RAM are detected by the bootstrap process. Here [1] you write that the older Beagleboard has only 128MB, so this is default setting. As described in that thread, I tried to create the Makeconf.boot file, and it works so far (image is build with 256MB RAM), but still only 128MB are actualy detected (limited by scan): L4 Bootstrapper Build: #30 Di 6. Sep 14:38:47 CEST 2011, 4.5.1 Scanning up to 256 MB RAM Memory size is 128MB (Limited by Scan) (80000000 - 88000000) RAM: 0000000080000000 - 0000000087ffffff: 131072kB Total RAM: 128MB Please see [2] for the full bootstrap log. I already tried to adjust manually the support.h and startup.cc file in the src/l4/pkg/bootstrap/server/src directory, resulting exactly the same issue. By the way, I think this is causing L4Android to fail during boot, since memory is not correctly allocated: android | l4x_setup_memory: Can't get main memory of 256MB! MOE: mem_alloc: quota: limit=-1 Byte, used=11572080 Byte MOE: mem_alloc: global: avail=57008128 Byte android | Terminating L4Linux. mag | GC: step this=0x108d220 _life = 0x13228 mag | GC: object=0x13228 Thank you for your help so far! Regards Giorgio [1] http://os.inf.tu-dresden.de/pipermail/l4-hackers/2011/004773.html [2] http://pastebin.com/nHQYGz6s

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Re: Sigma0 raised exception on boot
by Wesley Miaw 14 Sep '11

14 Sep '11

On Wed, 2011-08-03 at 20:51 +0000, Adam Lackorzynski wrote: > On Wed Aug 03, 2011 at 12:58:08 +0100, Anna Fischer wrote: > > I'm running Fiasco on the PandaBoard. On platform boot I'm getting an > > error that Sigma0 raised an exception and then Fiasco panics and the > > boot process stops. > > > > Any idea what the problem could be? I can't find any more information to > > debug this properly. I have compile Fiasco.OC and L4Re for the > > PandaBoard platform. The board has 1GB memory. > > > > KERNEL: Warning: Sigma0 raised an exception --> HALT > > Panic: ... > > Return reboots, "k" enters L4 kernel debugger... > > In src/kern/thread-ipc.cpp, before the message "Sigma0 raised an > exception", please add an 'ts->dump();' and retry. This should show more > info on what's going on. This is something that should definitely not > happen. I'm wondering if a solution was ever found to this problem? I am hitting the same error on my Versatile Express rev. D board. My dump output looks similar to Anna's, but with a different RAM base address: EXCEPTION: swi pfa=6009e00c, error=00200000 R[0]: 6009e00c 60096510 0000000f 60096710 6009e018 60002000 0000000f 00000001 R[8]: 60096510 00000000 00000000 00000000 00000000 61013704 27102178 ffffff04 Here's Anna's dump for comparison: EXCEPTION: swi pfa=8009e00c, error=00200000 R[0]: 8009e00c 80096b50 0000000f 80094dd4 8009e018 80002000 0000000f 00000001 R[8]: 80096b50 00000000 00000000 00000000 80096d48 81013044 45559145 ffffff04 This is happening as a result of the call to sigma0_thread->activate() inside kernel_thread-std.cpp. I haven't been able yet to track it down farther. Thanks, -- Wesley Miaw wesley(a)wesman.net

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Re: build error: No rule to make target crtendS.o
by Wesley Miaw 13 Sep '11

13 Sep '11

On Mon, September 12, 2011 09:45, Adam Lackorzynski wrote: > Hi, > On Mon Sep 12, 2011 at 08:38:56 -0700, Wesley Miaw wrote: >> Do you have any clues as to why I only get garbage printed out when I try to run one of the bootstrap programs? > Hmm, the baud-rate in bootstrap is set to 115200, so that's what you're using? IIRC the boot monitor is using 38400. Thanks, Adam. That was exactly the problem for why I was getting garbage. I didn't think to guess the bootstrap might be changing the console baud rate. I've tried changing the code to use 38400 instead of 115200 (because I can't find a way to change the board's startup to use 115200, only post-startup, which makes things inconvenient) but all of my attempts to change the values of 115200 to 38400 in the code don't seem to have any effect. I had to switch the RAM_BASE to 0x60000000 but after doing that, it looks like things should be working. I also changed the Fiasco globalconfig settings to change it to VEXPRESS and use 0x60000000 as the RAM location. I noticed there are two builds of Fiasco being created also. One of which is multi-core and has a TrustZone option. The other does not: arm-mp-rv-pb11mp and arm-up-rv-9. I'm not sure which one is getting used right now. Anyway, doing this got everything to load until the point where it says there is an invalid System ID. I'm guessing I still need to tweak the kernel configuration but at least I've made some good progress today! Starting kernel fiasco at 60001000 Realview System ID: Rev=3 HBI=190 Build=f Arch=5 FPGA=05 Invalid System ID for this kernel config Expected (3190f505 & ffffff00) == 1190f500 Stopping. Thanks for your help. :) -- Wesley Miaw wesley(a)wesman.net

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l4-hackers September 2011