l4-hackers February 2003

l4-hackers@os.inf.tu-dresden.de

10 participants
7 discussions

a article about l4 vm
by Yu Neil 28 Feb '03

28 Feb '03

hello: where i can find the article: "L4's Recursive Virtual Memory Model, Design and Implementation Issues of a L4 V4 Mapping Database" ? there is no link at www.l4ka.org Neil Yu _________________________________________________________________ 与联机的朋友进行交流，请使用 MSN Messenger: http://messenger.msn.com/cn

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(no subject)
by Yu Neil 24 Feb '03

24 Feb '03

hello: where i can find the ChacmOS , the old link http://l4ka.sourceforge.net/download/ChacmOS-src-RC1.tgz is unavailable, thanks a lot Neil Yu _________________________________________________________________ 享用世界上最大的电子邮件系统― MSN Hotmail。 http://www.hotmail.com

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RMGR Documentation needed
by Daniel Koch 24 Feb '03

24 Feb '03

Hello Is there any good Documentation on RMGR available ? I need to know how I can load modules into specific areas of memory, because I got some overlapping module problems, almost the same as mentioned in the list before. The solution with l4ka GRUB using the feature modaddr doesn`t work for me, cause I use a different architecture (Athlon K7, Reiserfs). RMGR: loading (hd 2,0)/sigma0 RMGR: loading kernel (hd 2,0)/main -nokdb RMGR:overlaps:00300000 - 0030239c: (hd 2,0)/main -nokdb RMGR: 00100000 - 001be980 module 02 : 00231000 - 0023256c: (hd 2,0)/rmgr.cfg.linux module 03: 0023200 - 0032eb14: (hd 2,0)/glinux.gz root=/dev/sda3 overlaps = 1, mem_high = 0x0fff0000 RMGR: overlapping modules #!rmgr ### this is an example RMGR config file ### first, some global settings # small address spaces have a size of 64 MB small_space_size 0x04000000 # wait for key press after initialization bootwait ### configuration for Sigma0 and RMGR follows # NOTE: it's generally useless to specify any resource allocation # constraints for Sigma0 and RMGR here: most will be ignored because # these tasks statically allocate all of their resources. That's why # we only specify bootstrap parameters here. task sigma0 boot_priority 100 task rmgr boot_priority 100 # enable next line if you want RMGR to run in small address space # 3 #boot_small 3 ### configuration for boot modules follows task modname "glinux" # make sure this entry # corresponds to a Linux server boot_small 2 # small address space # 2 boot_priority 100 boot_mcp 0x90 # maximum controlled priority log_mcp 0x90 # logical maximum controlled priority # -- useful if "boot_mcp 0" child max 512 in [10, 1023] # at most 512 child tasks in that range memory in [0, 0x02000000] # use only lower 32 MB RAM high_memory in [0xc0000000, 0xffffffff] # use only hi memory in that range small in [1,3] # allow these small address # spaces to be allocated # enable next line if you want to disallow allocation if IRQs 3 and 4 # (IRQs for serial lines COM2 and COM1) # irq mask 0xffffffe7 end menu.1st: gfxmenu (hd2,0)/message color white/blue black/light-gray default 0 timeout 8 title linux kernel (hd2,0)/vmlinuz root=/dev/sda3 vga=791 initrd (hd2,0)/initrd title Linux other root (hd1,0) makeactive chainloader +1 title floppy root chainloader +1 title failsafe kernel (hd2,0)/vmlinuz.shipped root=/dev/sda3 ide=nodma apm=off acpi=off vga=normal nosmp maxcpus=0 disableapic 3 initrd (hd2,0)/initrd.shipped title Fiasco + "hello world" root (hd2,0) kernel (hd2,0)/rmgr-fiasco -sigma0 module (hd2,0)/main-fiasco -nokdb module (hd2,0)/sigma0-fiasco #module (hd2,0)/glinux root=/dev/sda3 module (hd2,0)/hello-fiasco title L4-Linux #root (hd2,0) kernel (hd2,0)/rmgr -configfile -sigma0 module (hd2,0)/main -nokdb #modaddr=0x03000000 module (hd2,0)/sigma0 module (hd2,0)/rmgr.cfg.linux module (hd2,0)/glinux root=/dev/sda3 no-scroll module (hd2,0)/hello -- ------------------------------------------------------------------------------------ "Schlage die Trommel und fürchte dich nicht" (Heinrich Heine) Daniel Koch Berlin

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Ada run-time
by Nicholas Hannah 19 Feb '03

19 Feb '03

Hello, Is anyone interested in having the Ada run-time library running on L4? Has any work been done on this? I would consider contributing to an effort to get the core language going if there were others interested. I imagine it would be especially useful running on the StrongARM port of L4 for embedded systems development. chao, Nicholas

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Re: Deterministic scheduling with local APIC
by Jacob Gorm Hansen 05 Feb '03

05 Feb '03

On Wed, Feb 05, 2003 at 09:09:35AM -0800, Uwe Dannowski wrote: > If you want to account time, then why are you interested in counting > instructions executed? I believe the number of instructions is more or less > irrelevant (unless you want to schedule other resources than just time). > > You can use the IA-32 processors' performance counters to enforce an > interrupt (or an NMI) after a certain number of events, be it cycles, > instructions, memory accesses, FPU ops ... If you care just about user > time, you can configure them to count only when executing in user mode. This sounds perfect, I need to control exactly how many instructions a thread gets per time slice, no matter how many interrupts arrive at the CPU in the mean time, so that scheduling becomes deterministic. If a thread is interrupted by a hardware interrupt after fx half its time slice, I need to know exactly how many instructions it has already run, and need to be able to grant it exactly what is missing after the interrupt has been processed by the kernel. If I can do this I should be able to guarantee that two user programs running on two machines, receiving the exact same input, will be in the exact same state at the same (logical) point in time. That means one will be able to take over from another in case of failure. It seems to me one could augment one of the IA32 L4 implementations with this functionality, connect two machines with some kind of FIFO link, a good hub which sends all packets to both of them, and have failover solved at full speed, without need to rewrite any user level software. Maybe this has already been done though. But as always the use of a microkernel seems to make things simpler. > Uwe best, Jacob

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RE: Deterministic scheduling with local APIC
by Jacob Gorm Hansen 05 Feb '03

05 Feb '03

On Mon, 2003-01-13 at 16:06, Josh English wrote: > Jacob, Josh, I hope you don't mind me CCing this to the L4 list. > The largest problem I see with this scheme is that I cannot > conceive of a mechanism where the data sent to the CPU and > the failover CPU will not cause enormous delays. This is > because any failover system will require a confirmation of > the data received by the backup CPU. Even if the transport > and confirmation mechanism was hardware, the bottleneck > inherent in the design would render the system unfeasible in > a real-world implementation. I imagine that if the system is only ever accessed from the network, all the data that is to be duplicated comes from there. I suppose one could just use an Ethernet hub or similar hardware to make sure all Ethernet frames arrive at both hosts, coupled with a dedicated low-latency link between the hosts used for syncronisation (which given certain guarantees about the performance of the local Ethernet segment could be as simple as just each host counting all incoming frames and sharing the counter via the dedicated link). > Since my understanding of deterministic scheduling is that > in multiplicity scheduling, jobs are partitioned into > job types where the jobs in each type are identical. Then > the job is sent to any given machine as determined by the > scheduling mechanism. Thus sending every job to every > machine would cause much greater overhead than is justified > by having a failover mechanism. What I meant by 'deterministic' is just that all threads always get their full time slice. For this to happen a means of determining upon the arrival of an interrupt exactly how many cycles the running thread has left of its slice, and a means of granting it precisely this number of cycles before it gets preempted, is needed. I suppose you could use the TSC for the former and perhaps the local APIC for the latter, but I am unsure if trying to do so would be crazy. > Well, unless you are building systems to withstand nuclear > attack or something. So, if you want to write the code, I > think that your system would work provided your 'master' > scheduling mechanism resides above the kernel scheduler. > I think that this would prevent race conditions from > forming becuase hardware delays would be invisible to the > kernel at that point. I don't know if I will ever find time to write something like this, even if it were possible, but it struck me as an interesting future project. best, Jacob

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Re: Ada run-time
by Frederic BOYER 05 Feb '03

05 Feb '03

Hello Nicholas. I haved. In the past, I start the development of an QNX like OS on top of L4 written in Ada. All the servers were written in Ada (but used the pragma NO_RUN_TIME) The most difficult is to write the GNART (or GNULLI don't remember) of the GNAT compiler to directly use the L4 thread and memory managment. This project is in stand by for me. The main pb is that my HD which hosted the projects crash and I didn't do save :-( Give me news. Bye bye. Frédéric. Nicholas Hannah <nhannah(a)cse.unsw.edu.au>@os.inf.tu-dresden.de on 05/02/2003 07:25:24 Sent by: l4-hackers-admin(a)os.inf.tu-dresden.de To: l4-hackers(a)os.inf.tu-dresden.de cc: (bcc: Frederic BOYER/PARIS/CAI-Cheuvreux) Subject: Ada run-time Hello, Is anyone interested in having the Ada run-time library running on L4? Has any work been done on this? I would consider contributing to an effort to get the core language going if there were others interested. I imagine it would be especially useful running on the StrongARM port of L4 for embedded systems development. chao, Nicholas _______________________________________________ l4-hackers mailing list l4-hackers(a)os.inf.tu-dresden.de http://os.inf.tu-dresden.de/mailman/listinfo/l4-hackers "This message, including any attachments may contain confidential and privileged material; it is intended only for the person to whom it is addressed. Its contents do not constitute a commitment by Crédit Agricole Indosuez Cheuvreux except where provided for in a written agreement. Crédit Agricole Indosuez Cheuvreux assumes no liability or responsibility for the consequences arising out of a delay and/or loss in transit of this message, or for corruption or other error(s) arising in its transmission and for any misuse or fraudulent use which may be made thereof. If you are not the intended recipient, please contact us and abstain from any disclosure, use or dissemination. To the extent that this message contains research information and/or recommendations, these are provided on the same basis as Crédit Agricole Indosuez Cheuvreux's published research and the recipient must have regard to all disclosures and disclaimers contained therein."

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l4-hackers February 2003