l4-hackers October 2009

l4-hackers@os.inf.tu-dresden.de

6 participants
9 discussions

the preempter of one thread
by Guanghui, Cheng 30 Oct '09

30 Oct '09

Hi: Thread preempter is functional or ignored in the current fiasco. i read the lectures about microkernel-based operating systems and there are somethings about thread preempter. Thanks. Cheng Guanghui

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Some Errors in DDE
by Jingyi WANG 30 Oct '09

30 Oct '09

hi, I'm porting a sound card(ens1370)to DDE, but found some errors in the function of kobj_map whic is in map.c(l4/pkg/dde/linux26/contrib.drivers/base/map.c) What's more, I check the ELF format of this sound card.The error is in the address of 821607. The related messages show as follows: /home/wangjingyi/l4/tudos/l4/pkg/dde/linux26/contrib/drivers/base/map.c:58 mutex_lock(domain->lock); 821603: 8b 55 08 mov 0x8(%ebp),%edx 821606: 58 pop %eax 821607: 8b 82 fc 03 00 00 mov 0x3fc(%edx),%eax 82160d: 50 push %eax 82160e: e8 cd 65 02 00 call 847be0 <mutex_lock> I was wondering what caused this error and how to fix it. Thanks!

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ex_regs system call is forzed in the do_ipc process
by Guanghui, Cheng 23 Oct '09

23 Oct '09

Hello: When i use the ex_regs system call to trigger the exception ipc it seems to be frozed in the do_ipc stange. I use jdb to debug this current thread lists is like this: 9.04 l4ertl.exceptio 10 9.03 rcv,ipc_progr 9.03 l4ertl.timer0 10 9.02 rcv,ipc_progr 9.02 domain2.main 10 9.04 rcv,ipc_progr,exc_progr l4ertl.exceptio is the pager of domain2.main. And now l4ertl.timer0 is executing ex_regs system to trigger exception for domain2.main. l4ertl.exceptio is waiting for the exception ipc from the l4ertl2.main2. In detail l4ertl.exceptio is in ipc (user level registers). l4ertl.timer0 is in ipc (user level registers), too. domain2.main is in the exception 255. It seems to be dead lock in the kernel. Very strange. Thanks. Cheng Guanghui

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About some unimplement functions in DDE
by Jingyi WANG 20 Oct '09

20 Oct '09

Hi~When I run a device driver on DDE(pkg/dde/linux26/example), the result shows up that pci_set_master() and pci_disable_device is unimplement. Could you give me some advice on how to make these functions work?

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Re: About the exception ipc reply
by Guanghui, Cheng 16 Oct '09

16 Oct '09

On Wednesday 14 October 2009 06:52:10 you wrote: > On Tue Oct 13, 2009 at 13:01:46 +0800, Guanghui, Cheng wrote: > > On Monday 12 October 2009 02:03:41 Adam Lackorzynski wrote: > > > On Sun Oct 11, 2009 at 22:17:49 +0800, Guanghui, Cheng wrote: > > > > From the l4-x2 manual it is said the reply from the exception > > > > handler contains a label, an instruction pointer where the faulting > > > > thread is resumed. I want to know whether it is implemented in the > > > > Fiasco. I try to do this. Modify the utcb before send ipc resume the > > > > exception thread but it seems no any effect about the instruction > > > > pointer and stack pointer of resumed exception thread. > > > > > > My guess would be that you did not set the number of words to send in > > > the reply. Set L4_UTCB_EXCEPTION_REGS_SIZE in the msgtag-words field of > > > the reply. > > > > Hello Adam: > > Now i use L4_UTCB_EXCEPTION_REGS_SIZE and i could fix the thread with > > esp and eip by exception handler UTCB. And the thread could start with > > new instruction pointer and new stack pointer. But it still has some > > problem when the thread quit from new function. So i want to know how an > > thread is resumed by exception reply. I mean which part of code in kernel > > could finish the thread wakeup. I read the receive.c but i don't find it. > > The function copy_utcb_to_ts copies the state from the utcb of the > exception handler over the state of the thread. The thread then resumes > with this new state. I think what you have to do is to e.g. prepare the > stack of the thread in a way that when the new function's ret is > called it resumes at the position it was intercepted. Is this possible? Hello, Adam: Now the demo could work according to your design. And this demo is so simple only to emulate the situation we talked about before. I introduced a little about this demo: 3 threads: timer_thread, exception_thread, main_thread main_thread emulates the behaviour of system which is a endless loop to output. the function body is thread_func1. timer_thread emulates the behaviour of timer thread which could trigger the exception periodically. exception_thread emulates the behaviour of handling interrupt. The function body is exception_handler. When the timer_thread modify the status of main_thread with flag L4_THREAD_EX_REGS_RAISE_EXCEPTION. The main thread will be suspend and the exception_thread could get the exception ipc from main_thread. Exception_thread will modify the ESP and EIP in the utcb and then reply to main thread. The main thread will resume to the function about handling interrupt. When the handling interrupt function is over. The main thread could go back to the status before the exception happens. The output: count 49 ... count 58 id: 8:1, 12 0xeacff011 15 0x100711c do irq 0 ... do irq 9 l4_sleep(): IPC error 00 count 59 ... count 67 id: 8:1, 12 0xeacff011 15 0x100711c The output between "count ..." is execution of main thread. The output between "do_irq ..." is execution of exception thread which emulates the interrupt handling. BUT. I have a problem about my code when i fixing the stack of main thread. The correct code which could work well is like this: utcb = l4_utcb_get(); eip = utcb->exc.eip; esp = utcb->exc.esp; utcb->values[12] = (l4_umword_t)(do_irq); esp_loc = 1024 - (esp - (l4_umword_t)stack)/4; stack[esp_loc - 1] = eip; l4_msgtag ... l4_ipc_send_tag In the code above i only reset the next stack with return address (old eip). But it seems i can't reset the new stack pointer like utcb->values[15] = esp - 4 In my opinion it should do but if i did it can't work. It seems some tricky here. Can you tell me why it is like this? Additinally, i tried this way about handling interrupt with interrupt number like this: void do_irq(int irq) it can't work either. Thanks. Cheng Guanghui

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Split console with two keyboards
by Shakthi Kannan 16 Oct '09

16 Oct '09

Hi, I would like to know if it is possible in any of the L4* systems to have a setup like the following: * The console (framebuffer) to be split into two frames/windows, say top and bottom halves, but, each one should be used/accessed independently of each other. * With two keyboards connected to this single system, one should be able to use (shell) one of the keyboards with the top window, while the other should use the bottom one. Appreciate any thoughts/inputs in this regard. Thanks! SK -- Shakthi Kannan http://www.shakthimaan.com

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About the exception ipc reply
by Guanghui, Cheng 14 Oct '09

14 Oct '09

Hello: From the l4-x2 manual it is said the reply from the exception handler contains a label, an instruction pointer where the faulting thread is resumed. I want to know whether it is implemented in the Fiasco. I try to do this. Modify the utcb before send ipc resume the exception thread but it seems no any effect about the instruction pointer and stack pointer of resumed exception thread. Thanks. Cheng Guanghui

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Back to UTCB IPC
by Marc CHALAND 11 Oct '09

11 Oct '09

Hi, I am back with my problem with UTCB IPC. To sum up the context : I use pure l4env applications. Here is the scenario between my server and my client : 1. client makes an UTCB IPC to manager. Manager does an l4rm_area_reserve, creates a rcv_fpage, creates worker and sends back worker thread id to client. 2. client allocates memory and associated flexpage and sends it to server. 3. UTCB IPC is sent to worker with 3 parameters : - on client side : utcb->values=0xbff00200: arg1=0x2 arg2=0x1 arg3=0x6 - on server side : utcb->values=0xbff00200: arg1=0x241401 arg2=0x0 arg3=0x7069776c It seems that 0xbff00200 is not mapped on the same memory on client and server side. As there is no problem for first IPC (utcb->values is also 0xbff00200), is there any potential problem with flexpage ? As utcb->values is still the same, what happens if several threads try to make UTCB IPC ? Another question : when I link my application with liblogserver.a, I have strange logs : .rm.sem.mainMain function returned. It seems that .rm .sem and .main are added by l4env, but I didn't find where. Regards Marc

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Maybe we can use the two registers in the Exception IPC as Pagefault IPC
by Guanghui, Cheng 10 Oct '09

10 Oct '09

Hello: In the present implementation of exception ipc the two registers are not used but only given with 0. It seems a little bit waste. I mean in the page fault ipc the two registers include address where page fault occurs and instruction pointer which causes the page fault. Can we make exception ipc includes two registers with the next/current eip and esp? It seems not to be bad for this system call because it is a little bit strange that this exception ipc doesn't includes anything useful. Thanks. Cheng Guanghui

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l4-hackers October 2009