Hello everyone,
as part of a practical course at my university my group has to bring Fiasco.OC and L4re to the NanoPC-T3 Plus which is powered by the S5P6818 from Samsung/Nexell.
We’re currently stuck on multiple fronts, and as a sort of last resort I’m asking here for help, I hope you don’t mind.
1. Problem - The RAM
We implemented a working uart driver for our board and when using all (seemingly) correct values for the RAM region (as stated in the TRM is located from 0x40000000 to 0xc0000000) our SBC only boots up to the message “Hello from Startup::stage2” and then hangs in the function Kmem_alloc::Kmem_alloc() , we believe because the value of Map_base is with 0xffff000040000000 far too big but haven’t found a way to fix this issue whilst keeping the correct RAM region. Does someone have an idea why setting the incorrect RAM region results in more progress in the boot process (as stated in the following paragraph)?
2. The Timer - or the lack thereof
When we were experimenting with the RAM size we found that when setting to to 3GB starting from 0x40000000 we achieve slightly more output. Right up to ARM generic timer, which seems to not work on this particular board, we decided to implement our own timer driver, now we are stuck at Panic: Trace buffer size unaligned which, upon investigation, was an output from the JDB; by disabling the debugger we could again get more output, seen below. The clock doesn’t seem to start counting and I currently have no idea how to implement my own clock driver, I was hoping the generic clock would suffice.
Bytes transferred = 1223880 (12acc8 hex)
## Booting kernel from Legacy Image at 40080000 ...
Image Name: L4 Image #428
Image Type: AArch64 Linux Kernel Image (uncompressed)
Data Size: 1223816 Bytes = 1.2 MiB
Load Address: 41000000
Entry Point: 41000000
Verifying Checksum ... OK
Loading Kernel Image ... OK
Starting kernel ...
L4 Bootstrapper
Build: #428 Thu Jan 14 22:44:58 CET 2021, 7.5.0
RAM: 0000000040000000 - 00000000ffff0000: 3145664kB
Total RAM: 3071MB
Scanning fiasco
Scanning sigma0
Scanning moe
Moving up to 5 modules behind 41100000
moving module 02 { 410dd000-4112ac87 } -> { 411cb000-41218c87 } [318600]
moving module 01 { 410c4000-410dcea7 } -> { 411b2000-411caea7 } [102056]
moving module 00 { 41077000-410c34cf } -> { 41165000-411b14cf } [312528]
moving module 04 { 4103f000-41076bbf } -> { 4112d000-41164bbf } [228288]
moving module 03 { 41012000-4103ee4f } -> { 41100000-4112ce4f } [183888]
Loading fiasco
Loading sigma0
Loading moe
find kernel info page...
found kernel info page (via ELF) at 40003000
Regions of list 'regions'
[ 40000000, 400000ef] { f0} Root mbi_rt
[ 40001000, 40058fff] { 58000} Kern fiasco
[ 400f0000, 40108a5b] { 18a5c} Sigma0 sigma0
[ 40118a60, 4011c2ef] { 3890} Sigma0 sigma0
[ 40130000, 4017d4cf] { 4d4d0} Root moe
[ 4018d4d0, 40198d67] { b898} Root moe
[ 41000000, 41011193] { 11194} Boot bootstrap
[ 41100000, 41164fff] { 65000} Root Module
found kernel options (via ELF) at 40004000
Sigma0 config ip:401002bc sp:00000000
Roottask config ip:401413ec sp:00000000
Starting kernel fiasco at 40001818
Hello from Startup::stage2
Number of IRQs available at this GIC: 160
Detecting PSCI ...
Detected PSCI v1.1
PSCI: CPU_SUSPEND format extended, supports OS-initiated mode
PSCI: TOS: Not present or not required.
SERIAL ESC: allocated IRQ 7 for serial uart
Not using serial hack in slow timer handler.
Welcome to L4/Fiasco.OC!
L4/Fiasco.OC microkernel on arm
Rev: cffbd484-dirty compiled with gcc 7.5.0 for Samsung S5P6818 []
Build: #212 Thu Jan 14 22:44:36 CET 2021
Calibrating timer loop…
If anyone could maybe guide me into the right direction I’d be more than happy!
Thank you very much!
Best regards
Andreas
