On Mon, 2003-01-13 at 16:06, Josh English wrote:
> Jacob,
Josh, I hope you don't mind me CCing this to the L4 list.
> The largest problem I see with this scheme is that I cannot
> conceive of a mechanism where the data sent to the CPU and
> the failover CPU will not cause enormous delays. This is
> because any failover system will require a confirmation of
> the data received by the backup CPU. Even if the transport
> and confirmation mechanism was hardware, the …
[View More]bottleneck
> inherent in the design would render the system unfeasible in
> a real-world implementation.
I imagine that if the system is only ever accessed from the network, all
the data that is to be duplicated comes from there. I suppose one could
just use an Ethernet hub or similar hardware to make sure all Ethernet
frames arrive at both hosts, coupled with a dedicated low-latency link
between the hosts used for syncronisation (which given certain
guarantees about the performance of the local Ethernet segment could be
as simple as just each host counting all incoming frames and sharing the
counter via the dedicated link).
> Since my understanding of deterministic scheduling is that
> in multiplicity scheduling, jobs are partitioned into
> job types where the jobs in each type are identical. Then
> the job is sent to any given machine as determined by the
> scheduling mechanism. Thus sending every job to every
> machine would cause much greater overhead than is justified
> by having a failover mechanism.
What I meant by 'deterministic' is just that all threads always get
their full time slice. For this to happen a means of determining upon
the arrival of an interrupt exactly how many cycles the running thread
has left of its slice, and a means of granting it precisely this number
of cycles before it gets preempted, is needed. I suppose you could use
the TSC for the former and perhaps the local APIC for the latter, but I
am unsure if trying to do so would be crazy.
> Well, unless you are building systems to withstand nuclear
> attack or something. So, if you want to write the code, I
> think that your system would work provided your 'master'
> scheduling mechanism resides above the kernel scheduler.
> I think that this would prevent race conditions from
> forming becuase hardware delays would be invisible to the
> kernel at that point.
I don't know if I will ever find time to write something like this, even
if it were possible, but it struck me as an interesting future project.
best,
Jacob
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Hi!I'm trying to build fiasco kernel but i've run in
some troubles. After "make hello" it gives mes this
error:
../../../../../lib/x86_586/l4v2/libl4dbg.a(i386-stub.o)(.text+0xac3):
In function `getpacket':
/home/juan/os/l4/pkg/l4dbg/lib/src/OBJ-x86_586-l4v2/../i386-stub.c:526:
undefined reference to `strlen'
collect2: ld returned 1 exit status
In this file(i386-stub.c) "#include <string.h>" was
commented, so i uncommented but the problem still
persists.What am I doing wrong?Has …
[View More]anybody got this
problem?
Thanks in advance
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Hi
I am currently pondering about ways to implement time partitioning
in an L4 context, i.e. the idea is to distribute processing time
to subsystems (consisting of groups of tasks/threads) according
to predefined rules. Ideally, the underlying subsystems should
be unaware of this process. Also, ideally, the concept should
be recursive (i.e. a subsystem task should be able to donate
(some of) its processing time to other sub-subsytems).
At first glance, the concept of external preempters, as …
[View More]specified
(though AFAIK never implemented) in L4 looks like it could be a
useable basis for this, however:
- I'm still having difficulties to fully understand preempters
in L4. Their specification in the reference manual is somewhat
sketchy.
- I have a few ideas of my own, but implementing them would require
extensions to some L4 functions. My past experience with the L4
reference manual has been that everything in there is there for a good
reason, but the reasoning is not always explained (which is probably
the way a "reference manual" should be).
I would very much appreciate if someone could point me to a document
that explains the reasoning behind preempters, as defined in L4.
Failing that, are there any publications on external schedulers in
the context of microkernels that might be helpful to read, any discussion
forums you might suggest?
.. or am I really on uncharted ground here?
Any response would be greatly appreciated
Rob
----------------------------------------------------------------
Robert Kaiser email: rkaiser(a)sysgo.de
SYSGO AG
Am Pfaffenstein 14 phone: (49) 6136 9948-762
D-55270 Klein-Winternheim / Germany fax: (49) 6136 9948-10
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Hi experts,
I am trying to identify (and examine) ways to implement user-level scheduling
on L4.
I read in Michael Hohmuth's diploma thesis on L4Linux that it would have been
desirable to use the preemption handlers to implement Linux's scheduling
policy, but since L4 did not support them at the time, he used L4's built-in
scheduler instead.
Also I read a posting by Gernot Heiser in the mail archive of this list in
which he suggests that the preemption handler concept is somehow flawed.
…
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To my knowledge, none of the current L4 variants has implemented the concept.
To be honest, I'm having difficulty to fully understand the concept. For
instance, the difference between an internal and an external preempter is not
clear to me.
So my questions are:
- is there any further reading (besides the L4 Reference Manual and the L4
User Manual) that describes the concept ?
- has the concept actually been put to the test ?
- roughly, how would I implement a specific scheduling policy in e.g. L4Linux
based on this concept (assuming L4 does provide it) ?
Thanks in advance for any insights!
Rob
----------------------------------------------------------------
Robert Kaiser email: rkaiser(a)sysgo.de
SYSGO AG
Am Pfaffenstein 14 phone: (49) 6136 9948-762
D-55270 Klein-Winternheim / Germany fax: (49) 6136 9948-10
[View Less]
hi again,
[OT: First of all a great thanks to everyone at TU Dresden for the
interesting discussions and pleasant company during our visit last
week.]
Following a discussion with Jan Glauber Friday evening on the HP
Somersault API, which does failover by making sure processes on a
standby machine receive the exact same inputs as those on the master
machine, I wondered if anyone knows if the PentiumII local APIC is
precise enough that you can do completely deterministic scheduling, say,
in …
[View More]Fiasco?
It seems to me that one could implement an OS-level failover system by
wrapping the OS in an I/O environment (like NomadBIOS ;-)) which would
somehow ensure that the exact same input was received at both the master
and the slave hosts, provided that the scheduling performed by the
kernel scheduler could be performed with clockcycle precision (otherwise
race conditions would allow things to get out of sync).
Does anyone have an opinion as to whether or not this might be possible
using current Intel hardware?
best,
Jacob
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Hi
I'm interested in download the source of the Fore-PCA200 firmware the DROPs
project made (source code), and also the driver
I haven't found that on the guest access to the cvs server, etc...
I have tried to contact Uwe Dannowski and other L4-ATM people with no luck
anybody can help me?
Thanks in advance
Ulisses
Debian GNU/Linux: a dream come true
-----------------------------------------------------------------------------
"Computers are useless. They can only give …
[View More]answers." Pablo Picasso
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hello:
how current l4(with oskit) implement the driver framework? ( the oskit`s
? ), and where is the Omega0 server ? ( not implement ? )
Neil Yu
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