l4-hackers November 2015

l4-hackers@os.inf.tu-dresden.de

9 participants
11 discussions

Graphical desktop, l4con, mag
by teclis High Elf 02 Jun '17

02 Jun '17

Guten Tag, I've got the Hello app runing with fiasco and l4re in qemu, how do I get the graphical UI and console running that I see on the screen shots page? Do I need to use l4con and mag? I don't see an entry with l4con in modules.list. danke * <http://german.about.com/library/media/Audio/gutentag.wav>*

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libfs/ FUSE on L4Re
by Stark, Josef 31 May '17

31 May '17

Hello, yesterday I came across a very interesting paper titled "Porting FUSE to L4Re", accessible here: http://os.inf.tu-dresden.de/papers_ps/pester-beleg.pdf For porting FUSE, the author uses a library called "libfs" which provides filesystem request forwarding and processing, if I understood correctly. It reads as if libfs is already included in L4Re. However, I couldn't find neither FUSE nor libfs in the current L4Re snapshot. Are they by any chance publicly available somewhere else, or are … [View More]

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Hiring engineers for seL4 work
by Gernot Heiser 12 Jan '16

12 Jan '16

Do you want to be paid for contributing to the seL4 microkernel and its ecosystem, and getting your code used in critical systems on a large scale? As part of a kick-ass team, while living in Sydney, one of the world’s most liveable cities? The seL4 team at DATA61 (formerly NICTA) is hiring OS engineers, see https://ssrg.nicta.com.au/jobs/OS-engineers2015 We’re also hiring: - proof engineers: https://ssrg.nicta.com.au/jobs/proof-engineers2015 - researchers/postdocs: https://ssrg.nicta.com.au/jobs/OS-researchers2015 Gernot

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Question about memory management in L4 Fiasco O.C + L4re
by Mahdi Aichouch 04 Jan '16

04 Jan '16

Hello, I have some questions concerning memory management in Fiasco O.C + L4re. I would like to test two L4Linux instances, and for each L4Linux instance I want to reserve one static fixed physical memory partition. For instance, one 128MB for the first L4Linux and one 128MB for the second. Knowing that Fiasco O.C. uses "on demand paging" to allocate pages for user tasks, is it possible that each partition of L4Linux could be allocated a static physical memory region composed of contiguous … [View More]

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L4Re halts at boot, waiting for console input
by Arttu Pulli 28 Nov '15

28 Nov '15

Hello hackers, the subject line summarizes my problem pretty well. To expand, the halting happens first when Ned begins booting the user space services defined in the modules.list config, after it has loaded the Lua config script file. First I thought that my setup is just wrong, but feeding some amount of newlines through the serial console causes the boot to continue normally. The system is still waiting for input during this, though, as can be seen from the fact that the boot will go … [View More]

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Re: L4Linux update? Driver support
by li94575 28 Nov '15

28 Nov '15

At 2015-11-22 23:42:55, "Adam Lackorzynski" <adam(a)os.inf.tu-dresden.de> wrote: >hi, > >On Sun Nov 22, 2015 at 22:07:46 +0800, li94575 wrote: >> hello Adam, >> I also have a question about the Interrupt mechanism in l4linux. I want to move some interrupts to specified cpu core. When I try to write to "/proc/irq/*/smp_affinity" with cpu bitmask, it will call the function l4lx_irq_dev_set_affinity(), which attachs the irq to corresponding vcpu thread. After that, I … [View More]

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Qt on L4
by Nancy Joshua 27 Nov '15

27 Nov '15

Hi all i wanna port QT to l4.The documentation and tutorial in www.trolltech.com is not available any more. I have no idea how to start porting either. Any help in this regard is highly appreciated. -- Thanks and Regard Nancy Joshua

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QT on L4re
by Nancy 27 Nov '15

27 Nov '15

hi, am trying to port qt on l4re, but i wasn't able to find any qt resources in the tudos website.The documentation and tutorial from trolltech.com seem to have been removed. So any help in this regard will be appreciated. thank you Nancy Josh

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Problem when testing the "ex_isr" example on an ARMv7 Cortex-A9 based board.
by Mahdi Aichouch 16 Nov '15

16 Nov '15

Hello, I tried to run the "ex_isr" example on a Freescale i.MX6 Quad Cortex A9 Sabre SD board. And I got an error saying: "Binding IRQ1 to the ICU failed". Does someone has an idea of what might be wrong. Below is the trace from the "ex_isr" example, followed by my globalconfig.h file: Thank you very much in advance. Best regards, Mahdi L4 Bootstrapper Build: #53 Thu Nov 12 11:18:21 CET 2015, 4.8.3 20140320 (prerelease) Scanning up to 1024 MB RAM, starting at offset 32MB Memory … [View More]size is 1024MB (10000000 - 4fffffff) RAM: 0000000010000000 - 000000004fffffff: 1048576kB Total RAM: 1024MB Scanning fiasco Scanning sigma0 Scanning moe Moving up to 5 modules behind 11100000 moving module 02 { 110b4000-110ed63f } -> { 111a4000-111dd63f } [235072] moving module 01 { 110aa000-110b338b } -> { 1119a000-111a338b } [37772] moving module 00 { 11044000-110a97cb } -> { 11134000-111997cb } [415692] moving module 04 { 1102a000-11043597 } -> { 1111a000-11133597 } [103832] moving module 03 { 11010000-11029473 } -> { 11100000-11119473 } [103540] Loading fiasco Loading sigma0 Loading moe find kernel info page... found kernel info page at 0x10002000 Regions of list 'regions' [ 10000000, 100000e7] { e8} Root mbi_rt [ 10001000, 10001aff] { b00} Kern fiasco [ 10002000, 10072fff] { 71000} Kern fiasco [ 10090000, 10096edf] { 6ee0} Sigma0 sigma0 [ 10098000, 1009e177] { 6178} Sigma0 sigma0 [ 10140000, 10171d77] { 31d78} Root moe [ 10178000, 101934ab] { 1b4ac} Root moe [ 11000000, 1100f4ff] { f500} Boot bootstrap [ 11100000, 11133fff] { 34000} Root Module API Version: (87) experimental Sigma0 config ip:10090100 sp:00000000 Roottask config ip:10140260 sp:00000000 Starting kernel fiasco at 100012c8 Hello from Startup::stage2 Per_cpu_data_alloc: (orig: 0xf0062510-0xf0062ed8) Number of IRQs available at this GIC: 160 FPU0: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard, p: dbl/sngl L2: ID=410000c7 Type=9e340340 Aux=32070000 WMask=ffff S=0 L2: Type L2C-310 Size = 1024kB Ways=16 Waysize=64 SERIAL ESC: allocated IRQ 58 for serial uart Not using serial hack in slow timer handler. Welcome to Fiasco.OC (arm)! L4/Fiasco.OC arm microkernel (C) 1998-2013 TU Dresden Rev: rexported compiled with gcc 4.8.3 for i.MX6 [] Build: #192 Tue Nov 10 18:06:43 CET 2015 Per_cpu_data_alloc: (orig: 0xf0062510-0xf0062ed8) KERNEL: Warning: Buddy::alloc: Size mismatch: 9c8 v 1000 Allocate 2504 bytes (2KB) for CPU[4] local storage (offset=1187af0, 0xf11ea000-0xf11ea9c8) Number of CPUs: 4 Calibrating timer loop... Per_cpu_data_alloc: (orig: 0xf0062510-0xf0062ed8) done. KERNEL: Warning: Buddy::alloc: Size mismatch: 9c8 v 1000 Allocate 2504 bytes (2KB) for CPU[1] local storage (offset=1189af0, 0xf11ec000-0xf11ec9c8) MDB: use page size: 20 MDB: use page size: 12 SIGMA0: Hello! KIP @ 10002000 allocated 4KB for maintenance structures SIGMA0: Dump of all resource maps RAM:------------------------ [4:10000000;10000fff] [0:10073000;1008ffff] [0:10097000;10097fff] [0:1009f000;1013ffff] [4:10140000;10171fff] [0:10172000;10177fff] [4:10178000;10193fff] [0:10194000;110fffff] [4:11100000;11133fff] [0:11134000;4effffff] IOMEM:---------------------- [0:0;fffffff] [0:50000000;ffffffff] MOE: Hello world FPU1: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard, p: dbl/sngl MPer_cpu_data_alloc: (orig: 0xf0062510-0xf0062ed8) O KERNEL: Warning: Buddy::alloc: Size mismatch: 9c8 v 1000 E: fCache config: ON ouAllocate 2504 bytes (2KB) for CPU[2] local storage (offset=1140af0, 0xf11a3000-0xf11a39c8) nd ID_PFR[01]: 00001231 000000111031156 ID_[DA]FR0: 00010444 00000000 KID_MMFR[04]: 00100103 20000000 01230000 00102111 ByCPU[1]: goes to idle loop te free memory MOE: found RAM from 10000000 to 4f000000 MOE: allocated 1008 KByte for the page array @0x10194000 MOE: virtual user address space [0-bfffffff] MOE: rom name space cap -> [C:501000] BOOTFS: [11100000-11119474] [C:503000] l4re BOOTFS: [1111a000-11133598] [C:504000] ex_isr MOE: cmdline: moe --init=rom/ex_isr MOE: Starting: rom/ex_isFPU2: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard, p: dbl/sngl rPer_cpu_data_alloc: (orig: 0xf0062510-0xf0062ed8) Cache config: ON KERNEL: Warning: Buddy::alloc: Size mismatch: 9c8 v 1000 ID_PFR[01]: 00001231 00000011M ID_[DA]FR0: 00010444 00000000 OID_MMFR[04]: 00100103 20000000 01230000 00102111 EAllocate 2504 bytes (2KB) for CPU[3] local storage (offset=1144af0, 0xf11a7000-0xf11a79c8) : lCPU[2]: goes to idle loop oading 'rom/ex_isr' Binding IRQ1 to the ICU failed MOE: task 270000679 exited with 1 FPU3: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard, p: dbl/sngl Cache config: ON ID_PFR[01]: 00001231 00000011 ID_[DA]FR0: 00010444 00000000 ID_MMFR[04]: 00100103 20000000 01230000 00102111 CPU[3]: goes to idle loop /* * * Automatically generated file; DO NOT EDIT. * Fiasco configuration * */ #define CONFIG_PERF_CNT 1 #define CONFIG_BIT32 1 #define CONFIG_MP_MAX_CPUS 4 #define CONFIG_EXPERIMENTAL 1 #define CONFIG_ARM_CORTEX_A9 1 #define CONFIG_ARM_CACHE_L2CXX0 1 #define CONFIG_CAN_ARM_CACHE_L2CXX0 1 #define CONFIG_ABI "vf" #define CONFIG_CXX "g++" #define CONFIG_LABEL "" #define CONFIG_CAN_ARM_CPU_CORTEX_A9 1 #define CONFIG_ARM_ENABLE_SWP 1 #define CONFIG_ARM_V7 1 #define CONFIG_ARM 1 #define CONFIG_JDB 1 #define CONFIG_FPU 1 #define CONFIG_BSP_NAME "imx" #define CONFIG_SCHED_FIXED_PRIO 1 #define CONFIG_CONTEXT_4K 1 #define CONFIG_HOST_CC "gcc" #define CONFIG_MP 1 #define CONFIG_ABI_VF 1 #define CONFIG_NO_FRAME_PTR 1 #define CONFIG_ARM_V6PLUS 1 #define CONFIG_WARN_ANY 1 #define CONFIG_INLINE 1 #define CONFIG_SERIAL 1 #define CONFIG_PF_IMX_UART_NR 1 #define CONFIG_PF_IMX_UART_NR_1 1 #define CONFIG_PF_ARM_MP_CAPABLE 1 #define CONFIG_PF_IMX_RAM_PHYS_BASE 0x10000000 #define CONFIG_PF_IMX_6 1 #define CONFIG_XARCH "arm" #define CONFIG_CC "gcc" #define CONFIG_HOST_CXX "g++" #define CONFIG_ARM_CPU_ERRATA 1 #define CONFIG_PF_IMX 1 #define CONFIG_WARN_LEVEL 2 #define CONFIG_VIRT_OBJ_SPACE 1 #define CONFIG_ARM_EM_STD 1 [View Less]

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How is network stack implemented in Fiasco/l4Re
by Yuxin Ren 06 Nov '15

06 Nov '15

Hi, I have a few questions about network stack in Fiasco/L4Re. Is network stack implemented in the kernel or user level? If in user level, are different protocols (IP/TCP) implemented in a single server or different servers? If in different servers, how do they communicate with each other? Is there any example code to show how to use network? How to send and receive TCP or UDP packets? How can I set up the network environment on bare metal machine? Is there documentation or instruction? … [View More]

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l4-hackers November 2015