Hi,
Kernkonzept proudly announces the availability of a development version of the
Fiasco.OC microkernel on github [1]. It features a detailed history and will be
updated regularly. Those interested in exploring the latest changes can amend
the latest L4Re snapshot release (see [2]) with this development version.
We plan to release development versions of the build system and selected
userspace components in the weeks ahead.
So, let us know what you think.
Cheers,
Matthias.
[1] https://…
[View More]github.com/kernkonzept/fiasco
[2] https://l4re.org/download.html
--
Matthias Lange, matthias.lange(a)kernkonzept.com, +49-351-41 888 614
Kernkonzept GmbH. Sitz: Dresden. Amtsgericht Dresden, HRB 31129.
Geschäftsführer: Dr.-Ing. Michael Hohmuth
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Hi Folks,
L4Linux.org mentioned:
"Compared to monolithic Linux, there is a small performance tradeoff because of the µ-kernel architecture. However, the initial L4Linux has been somewhat optimized, and on L4/x86 it has a very acceptable slowdown of less than 4 % for any relevant load.
"
Any place can find more detail about the test?
And I'm very curious the L4Linux performance vs "using hardware virtualization on top of L4", have you made any comparison before?
--
Thank you!
Bob
Dear friends of the microkernel,
it's about time for another microkernel and alumni meetup to catch up on all
the developments of the last 6 months. Let's meet for a beer or two.
To find a date that fits the most people please visit
https://dudle.inf.tu-dresden.de/Microkernel_Meetup/
and add your preferred day.
Regards,
Matthias.
--
Matthias Lange, matthias.lange(a)kernkonzept.com, +49-351-41 888 614
Kernkonzept GmbH. Sitz: Dresden. Amtsgericht Dresden, HRB 31129.
Geschäftsführer:…
[View More] Dr.-Ing. Michael Hohmuth
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Hello,
I recently looked at the collection of patches accumulated when trying to get
the CI20 support to a functioning state, and I think I've brought them up to
date with the latest upstream repository version (r75). In doing so, I've also
tried to break them up into distinct parcels of functionality so that the less
interesting or less relevant patches can be ignored.
A page describing the patches can be found here:
http://www.boddie.org.uk/paul/L4Re-Fiasco.OC.html
None of these …
[View More]patches have changed since previous discussions on this topic.
The rdhwr instruction support I needed to add, for instance, is still done in
MIPS assembly language, fitting in with existing support for another variant
of that instruction.
Anyway, I thought it might be useful to put them somewhere with a description
for future reference. I've yet to get round to looking seriously at L4Re on
the CI20 again and it isn't likely to happen now before the end of the year.
Paul
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Hi all,
when a page fault occurs, does the Instruction Register contain the
actual instruction that caused the fault or the previous instruction? In
the former case, how can I access it? I need the opcode + the operands
(like source/target registers). I already have the memory address that
the instruction tried to access.
I'm on ARM A9, so only load/store instructions can cause a page fault.
I know that I could also look at the address where my IP is pointing to
and get the instruction …
[View More]from there, but I'm wondering which way would be
easier/better.
Cheers,
Josef
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