l4-hackers

l4-hackers@os.inf.tu-dresden.de

2827 discussions

Re: send/receive confusion
by gernot＠cse.unsw.edu.au 14 Mar '99

14 Mar '99

Edmundo, I think I now understand the source of your confusion. In the Intel version of the L4 manual (at least in my copy of Sep 96), on p25 where the "rcv descriptor" is explained, the option "mem" has the top 30 bits of the descriptor word as "*snd msg/4". That should, of course, read "*rcv msg/4". Also, further to what I wrote in my previous mail: GH> - one or more page mappings or grants, provided that GH> - the "m" bit is set in the send descriptor, and GH> - the beginning of the sender's direct string (starting with the GH> register part) contains at least one valid "send fpage", and GH> - the receive descriptor either has the form of a valid "receive GH> fpage", or points to a "message" struct containing a valid "receive GH> fpage", and GH> - there is no error The second last bullet should read: - the receive descriptor either has the form of a valid "receive fpage" and the "m" bit is set, or points to a "message" struct containing a valid "receive fpage", and Gernot -- Gernot Heiser ,--_|\ School of Computer Sci. & Engin. Phone: +61 2 9385 5156 / \ The University of NSW Fax: +61 2 9385 5995 \_,--._* Sydney, Australia 2052 E-mail: G.Heiser(a)unsw.edu.au v http://www.cse.unsw.edu.au/~gernot PGP fingerprint: 94 1E B8 28 25 FD 7C 94 20 10 92 E5 0B FF 39 8F

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implementations of L4
by Edmund GRIMLEY EVANS 12 Mar '99

12 Mar '99

I've been trying to find out about existing implementations of L4. Perhaps people could correct or add to what I have discovered: * The original L4 by Jochen Liedtke. Written in assebler. For i486 and i586. NOT FREE and therefore utterly useless :-) * L4/MIPS from Australia. Written in assembler? GNU. * L4/Alpha from Dresden and Australia. Written in assembler? Not yet released but probably GNU? * Fiasco from Dresden. Written in C++, and designed for portabilty rather than efficiency, but only runs on i486 and i586 at present. GNU. * A version of L4 for x86 from Dresden written in C. I saw this mentioned in the list archive. Is it really separate from Fiasco? * L4/ARM in assembler. Unfinished? I saw this in the archive, too. If this list could be corrected and completed, could it be put on the L4 website, with links, as it must be what a lot of casual readers are interested in knowing? Edmund

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486/Pentium version problems
by Edmund GRIMLEY EVANS 12 Mar '99

12 Mar '99

Following the instructions at os.inf.tu-dresden.de/fiasco/use.html I built Fiasco and the Hello World server worked. Excellent! Then I tried building L4-Linux and it didn't work ... Then I noticed that grub-ext2fs-floppy apparently already contains everything you need to run L4-Linux except for L4 itself. So I just copied the fiasco "main" that I had built onto the floppy image as supplied, hacked menu.lst a bit at random, and tried that. That didn't work either, but the thing that caught my attention was a message something like this: RMGR: L4/Pentium ... I was running this on a 486. So my questions are: Do the same executables (main, rmgr, sigma0, glinux.gz) run on both 486 and Pentium, or do different versions have to be built? If the latter, are the versions in grub-ext2fs-floppy supposed to work only on Pentium? If so, how can I build a version for 486 when compiling on a 686 machine? (And also, could the code be made to run on both? It would make life easier ...) Edmund

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24 Feb '99

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24 Feb '99

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Re: L4 Mapping question
by Michael Hohmuth 23 Feb '99

23 Feb '99

"Adam 'WeirdArms' Wiggins" <awiggins(a)cse.unsw.edu.au> writes: > What TID does the kernel use for its ipc to Sigma0 to request > memory mapping for kernel usage. L4/x86 uses task 1, local thread 0, for communication with Sigma0. The Fiasco kernel doesn't do any IPC operations on behalf of itself -- so no thread id here. Michael -- hohmuth(a)innocent.com, hohmuth(a)sax.de http://www.sax.de/~hohmuth/

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Re: L4 Mapping question
by Michael Hohmuth 23 Feb '99

23 Feb '99

Robert Kaiser <rob(a)sysgo.de> writes: > I was aware that the bookkeeping would have to be in the kernel, otherwise > flush couldn't work as described in the manual. Only, how does it work ? > > Theoretically, each task could map each of it's pages to up to 2047 other > tasks. So, the kernel would need to maintain ~2K entries per mapped page > and task. This can't be! The only explanation I can think of right now > is that the kernel allocates room for entries dynamically, assuming that > the actual number of required entries will always be far less than > the theoretical limit. But that would mean you can break the system > simply by doing a big enough number of mappings. Each mapping of a physical page from virtual address VA1 in a task T1 to VA2 in T2 is kept track of using a kernel data structure called ``mapping entry.'' This data structure is allocated dynamically, but from a fixed-size pool (where the size can be specified at compile time or boot time). It's true that you can break the system by establishing an excessive number of mappings. There are several ways to deal with that, but I don't think any of them has been implemented in the freely-available research kernels; one way is detailed in Jochen Liedtke et al.'s paper ``Preventing Denial-of-Service Attacks on a µ-Kernel for WebOSes'' which is available from <URL:http://os.inf.tu-dresden.de/papers_ps/jochen/Denhot.ps>. > On Mon, 22 Feb 1999, Volkmar Uhlig wrote: > > In the current L4-implementation of Jochen Liedtke, one mapping entry is 16 > > Bytes.The Alpha implementation (done by me) needs 32 Bytes per entry (64 > > bit address space - and a lot of trix). The Fiasco kernel does not use > > lists. They need about 4 Bytes per entry + an some overhead per frame (I > > left bevore it was finished) > > I am getting the distinct feeling that I am missing something > very simple :-(. So, at the risk of looking like a complete fool: > How do you keep track of up to 2K tasks in a 16 Byte entry ? The 16-bytes structure is what I described as a ``mapping entry'' above. Mapping entries belonging to one physical page are linked to each other in a binary-tree structure using pointers. Michael -- hohmuth(a)innocent.com, hohmuth(a)sax.de http://www.sax.de/~hohmuth/

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Re: L4 Mapping question
by Michael Hohmuth 23 Feb '99

23 Feb '99

vuhlig(a)us.ibm.com writes: > The idea is, that the kernel can revoke pages from sigma 0, what is not > implemented yet. [...] I don't think it is a part of the Sigma0 specification that Sigma0 should be able to handle the case where the kernel revokes mappings of pages mapped into Sigma0. Instead, Sigma0 is pretty safe to assume that it magically owns---and has access to---all physically- addressable memory (maybe with the exception of the kernel-private code and data sections; the experts are still out on this one). Michael -- hohmuth(a)innocent.com, hohmuth(a)inf.tu-dresden.de http://home.pages.de/~hohmuth/

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Re: L4 Mapping question
by Michael Hohmuth 23 Feb '99

23 Feb '99

I wrote: > The resource manager Rmgr (which is normally used to startup L4/x86 > and Fiasco) handles the nitty-gritty details of telling the kernel > where it should find its Sigma0 server. In order to avoid any confusion: In a typical booting scenario on the x86, the Rmgr bootstrappig code runs even before the L4 or Fiasco kernel has been started. It is invoked directly by the boot loader and handles all initializations to be done before the kernel starts up: It finds the raw ELF binaries for the kernel and Sigma0 which the boot-loader has dropped in memory, interpretes them (i.e., moves them to their load addresses), configures the kernel (e.g., tells it the location of Sigma0 and Rmgr task entry points), and starts it. For more information, please read the Rmgr manpage at <URL:http://os.inf.tu-dresden.de/L4/l4libman/rmgr.html>. Michael -- hohmuth(a)innocent.com, hohmuth(a)sax.de http://www.sax.de/~hohmuth/

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L4 Mapping question
by Robert Kaiser 23 Feb '99

23 Feb '99

Hi all, I have a question regarding mapping in L4: I read in the L4 reference manual that Sigma0 maps each page only once. It does allow multiple mappings of a page to the same address space (i.e. task), but it does not allow multiple mappings to different tasks. Is this a specific feature of Sigma0 or is this true of all pagers ? I'm asking because I wonder how the fpage_unmap operation works: If a task is allowed to map a page to an unlimited number of different tasks (i.e. 2047 as there are up to 2048 tasks), then the bookkeeping involved in implementing fpage_unmap would require that a pager would theoretically need to keep track of up to 2047 tasks per page in order to allow fpage_unmap to revoke all mappings of a particular page. That looks like a tremendous overhead, so there must either be some limit to the number of mappings or there is something else I'm missing. Could someone please enlighten me about this ? Thanks in advance Rob ---------------------------------------------------------------- Robert Kaiser email: rkaiser(a)sysgo.de SYSGO RTS GmbH Carl-Zeiss-Str. 41 phone: (49) 6131 9138-80 D-55129 Mainz / Germany fax: (49) 6131 9138-10

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