On Mon, 2003-01-13 at 17:16, Jacob Gorm Hansen wrote:
On Mon, 2003-01-13 at 16:06, Josh English wrote:
What I meant by 'deterministic' is just that all threads always get their full time slice. For this to happen a means of determining upon the arrival of an interrupt exactly how many cycles the running thread has left of its slice, and a means of granting it precisely this number of cycles before it gets preempted, is needed. I suppose you could use the TSC for the former and perhaps the local APIC for the latter, but I am unsure if trying to do so would be crazy.
Well, unless you are building systems to withstand nuclear attack or something. So, if you want to write the code, I think that your system would work provided your 'master' scheduling mechanism resides above the kernel scheduler. I think that this would prevent race conditions from forming becuase hardware delays would be invisible to the kernel at that point.
It seems my idea is similar to the HP Hypervisor project by Bressoud and Schneider (1996). However, their effort benefited from the presence of a 'recovery register' on the PA-RISC. This register counts completed instructions rather than cycles, and allows you to implement deterministic scheduling (though that is not their exact approach). I cannot find info on a similar register in P3 or P4, does anyone know if it exists? If not, is anyone aware of other modern CPUs which sport such a register? My guess is that the Itanium might have one due to its PA-RISC heritage.
I am afraid that just relying on the TSC will lead to unpredictable results on a modern CPU.
Best, Jacob