Hi,
Thought I might be able to contribute something to this discussion. I am a PhD student at the University of York (UK) , Real-Time Systems research group and I've been looking at portability/ real-time / microkernels for the past year and half.
Our main interest is hard-real-time/ safety critical for applications in aircraft and suchlike. I studied the L4 kernel API/ paradigms and although my main interest is research (ie. towards a PhD!!) have started a partial port to a PowerPC 603e based on the MIPS port by Kevin Elphinstone:
http://www.cse.unsw.edu.au/~disy/L4/MIPS/
I chose this route because of the similarity of the two architectures and the wide availability of documentation for this kernel port. There is a document (Inside L4/MIPS) that documents a lot of the important parts of the code, especially low-level stuff (IPC path, system calls, memory management) and explains the architecture dependant design decisions/optimsations/restrictions. It is used actively at the university for teaching and research so there is always likely to be help available.
I was an absolute novice at the beginning of this and for an experienced OS implementor with experience of the architecture that the implementation is for then I wouldn't expect an implementation to take longer than 6 man months. For what its worth here is the strategy I followed:
* Look at my requirements ie. Flexible memory management for hard tasks. Minimal restrictions to application developers.
* Spend some time understanding the L4 kernel paradigm / API. Particularly with respect to IPC / fpage mapping.
* Understanding the design / implementation decisions used in the particular implementation (MIPS)
* Understanding the target architecture / machine. eg for memory management design. Does it have a fixed pagetable lookup algorithm?
* Sketch the design for the target architecture. There may be kernel API changes. For instance I separated tasks into threads/ address spaces as some L4 people have suggested will be done in the future.
* Looked at code resuse. I resued the page table lookup code (C) from L4/MIPS with virtually no changes. I resued (sort of) the assembler by an almost 1-1 mapping between instruction sets.
* Documented all design decisions / implementation decisions right through to assembler because its the only way I (or anyone else) would know what the hells going on!!
The trouble with this top down approach is that a lot has to be done before you get any working code. I found the MMU stuff could be done seperately (because I needed to get some results for a paper.
I have no experience in how Fiasco differs from L4/x86 but supporting HRT systems has implications for a new implementation. I have recently published a conference paper (ECRTS 01) on supporting virtual address spaces for Hard-Tasks on the PowerPC and have suggested solutions for a number of other architectures. (Apologies for the unashamed promotion of my own work :-) email me if you would like a copy) There are a number of other issues to do with IPC and scheduling.
Oh dear this has turned into a very large mail.
Cheers
Mike
http://www-users.cs.york.ac.uk/~mikeb/index.html
with may have some useful info. on it in the future (or perhaps not)
Martin Young (my@siroyan.com) said:
Michael Hohmuth wrote:
Martin Young my@siroyan.com writes:
I'm interested in putting L4 on a 'new' processor core [...].
Cool! Can you elaborate on why you're interested in doing this?
I work, as an OS developer, for a company which is producing said new core. It looks like we're going to have a non-MMU-capable tiny OS and a much heavier slower microkernel. I'd like us to also have an MMU-capable microkernel with a smaller footprint and better perforance. I don't have any particular application in mind.
Is there a recommended route for doing this?
Therefore, I personally would look into porting Fiasco. [with explanation of why]
I've downloaded the source of two implementations now (L4ka an Fiasco) and all the docs I can find. I'll proably spend a little while looking at these things then try to work out which code base makes most sense to me.
Thanks for your help.
-- Martin Young, working for: | Phone: +44(0) 1454 615151 Siroyan Limited, Bristol Design Centre, | Mobile: +44(0) 7855 758771 West Point Court, Great Park Road, | web: www.siroyan.com Bradley Stoke, Bristol BS32 4QG. UK | email: my@siroyan.com
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