Farid,
2.2: l4-ka/kernel/include/x86/cpu.h:enable_super_pages() ........................................................
INLINE void enable_super_pages() { __asm__ __volatile__ ("mov %%cr4, %%eax\n" "orl $0x10, %%eax\n" "mov %%eax, %%cr4\n" : : : "eax"); }
====> Turning on bit 4 of CR4 (PSE) enables 4 MB pages. ====> Volkmar: In Section 3.6.2.2 (at the End), the note says ====> Volkmar: that the TLBs _must_ be flushed (invalidated) after setting ====> Volkmar: or clearing the PSE bit. Forgot to do it?
====> This is the instruction that crashes bochs.
In l4-ka/kernel/src/x86/init.c directly after enable_super_pages: --------------------- snip -------------------- /* Load ptroot. */ set_current_pagetable(pdir_root);
enable_paged_mode(); --------------------- snip --------------------
At the mentioned point we are not in paged mode yet. Thus, it is not necessary to flush the TLB.
Volkmar
-- Dipl. Inf. Volkmar Uhlig, University of Karlsruhe, Dept. of CS, System Architecture Group 76128 Karlsruhe, Germany phone: +49 (172) 352-8285, fax: +49 (721) 608-7664, mailto:volkmar@ira.uka.de