Michael Hohmuth wrote:
Martin Young <my@siroyan.com> writes:
I'm interested in putting L4 on a 'new' processor core [...]. Cool! Can you elaborate on why you're interested in doing this?
I work, as an OS developer, for a company which is producing said new core. It looks like we're going to have a non-MMU-capable tiny OS and a much heavier slower microkernel. I'd like us to also have an MMU-capable microkernel with a smaller footprint and better perforance. I don't have any particular application in mind.
Is there a recommended route for doing this? Therefore, I personally would look into porting Fiasco. [with explanation of why]
I've downloaded the source of two implementations now (L4ka an Fiasco) and all the docs I can find. I'll proably spend a little while looking at these things then try to work out which code base makes most sense to me. Thanks for your help. -- Martin Young, working for: | Phone: +44(0) 1454 615151 Siroyan Limited, Bristol Design Centre, | Mobile: +44(0) 7855 758771 West Point Court, Great Park Road, | web: www.siroyan.com Bradley Stoke, Bristol BS32 4QG. UK | email: my@siroyan.com ********************************************************************** This email and any files transmitted with it are confidential and intended solely for the use of the individual or entity to whom they are addressed. If you have received this email in error please notify the system manager. This footnote also confirms that this email message has been swept by MIMEsweeper for the presence of computer viruses. www.mimesweeper.com **********************************************************************