Hi all,
Forgive me if this is a silly question because it is documented somewhere, but I am unfamiliar with Fiasco source, and too in a hurry to go through all the Fiasco source code and cross-comare it with the documentation/papers/examples etc....
Skimming though Fiasco source code I checked out few weeks ago (the Doxygen online version is from 2005, out of date), I found 16 "Proc::preemption_point();" in the IPC path in the source file thread-ipc.cpp:
[sergio 19:41 ~/Desktop/FIASCO/tudos/kernel/fiasco/src/kern]$ grep Proc::preemption_point thread-ipc.cpp | wc -l 16
Which tudos/kernel/fiasco/src/drivers/processor.cpp defines as:
... static inline void preemption_point() { sti(); irq_chance(); [ NOP NOP ] cli(); } ...
My question is:
As far as I know, Fiasco is entirely preemptable. Then why sprinkling the IPC path with Enable IRQs/NOP NOP/Disable IRQs ?
Is there a document or a paper that discuss which parts of the kernel run with IRQs disabled / enabled ? Preemption disabled / enabled etc. ?
Thanks in advance,
Sergio
On Thu, 2007-06-21 at 22:57 +0200, Sergio Ruocco wrote:
My question is:
As far as I know, Fiasco is entirely preemptable. Then why sprinkling the IPC path with Enable IRQs/NOP NOP/Disable IRQs ?
Is there a document or a paper that discuss which parts of the kernel run with IRQs disabled / enabled ? Preemption disabled / enabled etc. ?
In particular, the Fiasco IPC path for register only IPC runs with disabled interrupts and has explicit preemption points. The work of Rene Reusner (unfortunately in German) describes the trade-off between preemptability and performance of the IPC path.
http://os.inf.tu-dresden.de/papers_ps/reusner-diplom.pdf
Alexander Warg wrote:
In particular, the Fiasco IPC path for register only IPC runs with disabled interrupts and has explicit preemption points.
Then everything else in Fiasco runs with interrupts enabled and it is preemptable. Is this correct ? Are there notable exceptions ?
The work of Rene Reusner (unfortunately in German) describes the trade-off between preemptability and performance of the IPC path. http://os.inf.tu-dresden.de/papers_ps/reusner-diplom.pdf
Very interesting. It would be good to have an English translation of this thesis, or a paper based on it.
Thanks a lot for the prompt and informative answer,
Sergio
On Fri Jun 22, 2007 at 09:37:21 +0200, Sergio Ruocco wrote:
Alexander Warg wrote:
In particular, the Fiasco IPC path for register only IPC runs with disabled interrupts and has explicit preemption points.
Then everything else in Fiasco runs with interrupts enabled and it is preemptable. Is this correct ? Are there notable exceptions ?
No.
Adam
l4-hackers@os.inf.tu-dresden.de