l4-hackers January 1999

l4-hackers@os.inf.tu-dresden.de

14 participants
30 discussions

L4-Linux fails to boot - hangs setting up IDT
by Paul Phillips 14 Jan '99

14 Jan '99

I am trying to boot L4-Linux using the Fiasco microkernel. The microkernel boots fine, but when L4Linux is booting, in module chead.c you have the code: /* create idt */ { extern long idt_table; struct entry_t {unsigned short w0, w1,w2,w3;} ; struct entry_t *entries = (struct entry_t *)((unsigned long)emu_lib_text + ((unsigned long)&idt_table - EMULIB_CODE_ADDRESS)); unsigned short int tmp; int i; for (i=0; i<20; i++, entries++) { tmp = entries->w1; entries->w1 = entries->w3; entries->w3 = tmp; } } My system hangs when it attempts to execute this code. I understand why you are swapping the shorts in the table (swapping the offset bytes with the selector bytes) but there are a couple of things I don't understand Several questions: 1.) Why are you calculating the address of the table by subtracting out EMULIB_CODE_ADDRESS (Which is 0xA0008000?) ? 2.) How & why is the emulator code moved to "special page". Where is the "special page" set up since paging isn't set up until after this code is executed? 3.) Any clue why this is hanging here? I should have a remote debugger set up soon, but I have -nokdb set and I don't get any kernel panics or reg dumps. The system just hangs. Thanks in advance!! Paul Phillips

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Re: TCB size in ix86 L4
by Torsten Paul 08 Jan '99

08 Jan '99

Michael Hohmuth <hohmuth(a)innocent.com> writes: > can't meet real-time requirements; the task_delete operation seems to > be especially bad, sometimes disabling interrupts for more than one > second. > Yes, the measurements showed interrupt a latency of sometimes 1.5 seconds (even if the interrupt thread had the highest priority) when in the L4-Linux System had to serve a lot of calls to fork/exec. This was tested with the lat_proc benchmark from the lmbench-suite that tries to measure the latency for creating simple processes (that only call exit) Still there is only one explanation for this: disabled interrupts while flushing the complete address space of a task when doing task_delete. ciao, Torsten. -- Torsten Paul Es ist leichter, einen Atomkern zu paul(a)os.inf.tu-dresden.de // spalten als ein Vorurteil. __________________________ooO_(+ +)_Ooo________Albert Einstein_(1879-1955) U

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Re: next-gen mapping
by Michael Hohmuth 08 Jan '99

08 Jan '99

"Adam 'WeirdArms' Wiggins" <awiggins(a)cse.unsw.edu.au> writes: > Would an assembler based L4 benifit from this new mapping tree > data base too? It certainly sounds easier to handle memory for. I think that the binary-tree representation is easier to implement than the trees-in-fixed-size-arrays one. One factor which complicates the latter is that the fixed-size arrays have to be efficiently allocated, deallocated, and moved around in memory. Lukas' implementation includes a generic slab allocator for tree allocation. > I'm trying to work out my dynamic data structures now. So far i have > TCB's (512 bytes), 1st level page table entries 16K, 2nd level page > table entries 1K, mapping tree nodes ??? no idea yet. I got Lukas's > paper but i failed german in my high school years :( I'm trying to > get it translated. It there any code somewhere i can look at which > would illistraight it? Or does lukas have the time to give me an > english run down? I think Gernot is trying to translate the paper using Babelfish; Lukas has sent him his paper's sources. Other than that, I'm positive that we can help you understanding it. (If you're patient enough, you might even just wait until I've finished my technical report about Fiasco's design -- but don't hold your breath, please. :) Michael -- hohmuth(a)innocent.com, hohmuth(a)sax.de http://www.sax.de/~hohmuth/

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Re: TCB size in ix86 L4
by Michael Hohmuth 07 Jan '99

07 Jan '99

Adam, thanks for your replies! "Adam 'WeirdArms' Wiggins" <awiggins(a)cse.unsw.edu.au> writes: > Question here. Is Jochen's L4 got higher interupt latencies then > fiasco due to masking out interupts or is time in the kernel small enough > for real time applications. Our measurements with L4/x86 version 2 indicate that this kernel is not suitable for real-time work. The ``Taming Linux'' pager details some of these concerns <URL:http://os.inf.tu-dresden.de/papers_ps/part98.ps>. Recently, Torsten Paul did a series of measurements which show that L4/x86 often can't meet real-time requirements; the task_delete operation seems to be especially bad, sometimes disabling interrupts for more than one second. (Torsten, if you're reading this: Is this data correct?) Real-time requirements in our DROPS system are one reason why Fiasco tries to be interruptible at almost any time. Michael -- hohmuth(a)innocent.com, hohmuth(a)inf.tu-dresden.de http://home.pages.de/~hohmuth/

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Re: TCB size in ix86 L4
by Michael Hohmuth 06 Jan '99

06 Jan '99

[ As a courtesy to new readers: TCB = "thread control block", the kernel data structure holding thread-specific data including the thread's stack. ] "Adam 'WeirdArms' Wiggins" <awiggins(a)cse.unsw.edu.au> writes: > I was woundering why the TCB size in ix86 L4 is 1K, how much of > the stack at the end of the TCB is actually used? Very little: Most of the time, less than 150 bytes. > Could the TCB be reduced to 512K? If not why not? ^^^^ 512 bytes? I think it could. L4/x86 has disabled hardware interrupts most of the time, so the theoretical maximal stack usage probably isn't much higher than the one we see, maybe 100 bytes more. I guess Jochen didn't know it was so little when he designed L4, and never changed it later. In the Fiasco kernel, things are different: This kernel had been written in C++, and it may be interrupted at almost any time; handlers may interrupt each other and stack up on one thread's stack. That's why the theoretical maximal stack usage is much higher. Although I haven't computed it yet, I have estimated that a < 1K stack is too small for the current implementation. That's why Fiasco by default is configured to use 2-KByte TCBs. Michael -- hohmuth(a)innocent.com, hohmuth(a)sax.de http://www.sax.de/~hohmuth/

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Re: ARM/L4
by Michael Hohmuth 06 Jan '99

06 Jan '99

"Adam 'WeirdArms' Wiggins" <awiggins(a)cse.unsw.edu.au> writes: > I've started work on writting an assembler (perhaps with some C) > version of L4 for ARM version 4 starting with the StrongARM SA-1100 (on > the Brutus evaluation platform and some custom hardware). > If anyone is interested in the port or has started their own and > has any advice or suggestion please contact me. > At release time it will be covered by the GPL. That's great! Are you doing this out of sheer fun, or do you have in mind a specific application? Michael -- hohmuth(a)innocent.com, hohmuth(a)inf.tu-dresden.de http://home.pages.de/~hohmuth/

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Re: next-gen mapping
by Michael Hohmuth 06 Jan '99

06 Jan '99

"Adam 'WeirdArms' Wiggins" <awiggins(a)cse.unsw.edu.au> writes: > Can anyone explain whats different/new about the planned > next-generation mapping tree for fiasco? I'd appreciate a detailed > explination if anyones got the time. The new thing about the new mapping database is that its data structures are much smaller. It uses compact linear arrays of fixed sizes, instead of elements linked in binary trees, to store the mapping trees for a given physical page frame. The size of the current mapping database implementations (in L4/x86 and Fiasco) can become a severe problem: To support a heavily-loaded L4Linux, one eighth of the main memory has to reserved for mappings. This also has performance implications, as our AIM multiuser benchmark measurements show: If we steal original (monolithic) Linux one eighth of its main memory, the application-level performance penalty between Linux and L4Linux decreases from 3.8 percent to 2 percent (on our hardware). Michael -- hohmuth(a)innocent.com, hohmuth(a)inf.tu-dresden.de http://home.pages.de/~hohmuth/

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Re: Some questions about Fiasco
by Michael Hohmuth 06 Jan '99

06 Jan '99

Benjamin Gerfelder <benjamin(a)dante.saar.de> writes: > I just succeeded in booting Linux on Fiasco. Just in case anyone > is interested, here are the warnings I got while booting: [ warning messages appended below for reference ] Congratulations for getting it up! All of the bootup warning messages are normal (and probably should be removed from the code base). > [...] I just get *a lot of* > > wake_idle_if_needed: ipc failed > > messages, but this seems to be no problem. We decided to not remove this L4Linux warning message in this release because we think it hints at a potential problem; at least we don't get this message under Jochen's L4/x86. I have to discuss this some more with my colleagues... > The only thing I`ve found that doesn`t work is XFree86, when I try > to start it, the machine freezes with blank screen. A remote debugger or a second (Hercules) video card would be of help here. One idea I have is that maybe we don't see these hangs because we let Fiasco send the "ipc failed" warning messages to the Hercules screen instead of the VGA console. Perhaps XFree86 crashes when someone else fiddles with the video memory? I'll try this out. > 1) Are there any documents you suggest reading, besides the L4 Reference > Manual? Any document would be of use, since I don`t have a clue on > L4, but I want to play around with it. Is there anything like > "L4 for dummies" ? :) UNSW has an L4 User's Guide which covers MIPS L4, but some people have said it's interesting from an x86 perspective, too; see <URL:http://www.cse.unsw.EDU.AU/~disy/L4/l4uman.ps.gz>. Other than that, I suggest you read some (depending on your interest) papers about L4 and L4Linux at <URL:http://os.inf.tu-dresden.de/pubs/#l4linux>. Unfortunately, something like an ``L4 for dummies'' doesn't exist. > 2) Is Fiasco capable of running multiple servers at once? Yes, this is possible. > I tried to start two instances of this helloworld-server, but it > crashed immediately. This doesn't work because Rmgr, the boot-up server and resource manager, is not a sophisticated memory manager. It can only run servers which want a one-to-one physical-to-virtual virtual-memory- space mapping. You example would work if the two instances of "hello" were linked to different virtual memory locations. As an example which works out of the box, try running "hello" and the L4Linux server parallelly. > 3) Is there a simple way to reboot the system after Fiasco startet? > My Laptop has no reset button :) No, there isn't, unless your program does it for you. For instance, L4Linux uses the keyboard controller method to reset the machine when it shutdowns; this arguably is not the ``correct'' solution to this problem. Does anyone have a good idea for an interface to reset the machine in the normal and exceptional cases? Greetings, Michael > ----------------------------------- > Welcome to Fiasco! > DD-L4/x86 microkernel (c) 1998 TU Dresden - Dec 24 1998 > linux_startup > checking OFFS_TSS: ok, OFFS_TSS still 536 > detect processorsetup_paging > end linux_startup, calling start_kernel > setup_arch > sigma0 denies mapping of address 00001000 > No kernel code/data > sigma0 denies mapping of address 00002000 > No kernel code/data > [...] > sigma0 denies mapping of address 00149000 > No kernel code/data > > mb4 already requested > > 4m page received > sigma0 denies mapping of address 00ccc000 > No kernel code/data > > Memory end: 00ccc000 > > kernel info page mappt to: 00001000 > root: rcvd 2, 424a25 > Hmm, strange, that shouldn't happen anymore > Root: null pointer deref in 5.3 at addr: 2 and eip: 424a25 (pte: 27) > ------------------------------------- -- hohmuth(a)innocent.com, hohmuth(a)inf.tu-dresden.de http://home.pages.de/~hohmuth/

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next-gen mapping
by Adam 'WeirdArms' Wiggins 05 Jan '99

05 Jan '99

Can anyone explain whats different/new about the planned next-generation mapping tree for fiasco? I'd appreciate a detailed explination if anyones got the time. Cheers Adam

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Re: About external preempters
by Harald Fritzsche 03 Jan '99

03 Jan '99

Hello, it seems to me that external preempters are usefull for future use? So i have grabbed some information from the list and other sources. > [SH: S. Houidek]Hello, > > I have finished reading the L4/x86 reference manual, > and I have some questions about preempters : > > (1) What are the exact purposes of external and > internal preempters ? (See the L4 User manual from http://www.cse.unsw.edu.au/~disy/.) There exist (exclusivly?) only one internal preempter, wich is invoked after each timer interupt if the timesclice of running thread is expired or if it is called directly by kernel or user (l4_thread_switch or similar). This internal preempter is essential for the system itself. The scheduling is done by the thread_t::schedule() funtion in fiasco. External preempter: That is not a really preempter, its a user level scheduler. The preemption is done by the kernel described above. The External preempter is scheduled by the kernel if no task/thread with higher priority is ready. The intended purpose of an external preempter is to refine the kernels scheduling method with any user level method. There are 2 syscalls intended for use in external preempters, (i) l4_thread_switch and (ii) l4_thread_schedule. There are 5 variables, 1(3) syscall(s) and 1 ipc related to preemption/scheduling: (1) time_slice (2) priority (3) maximum controlled priority (4) external preempter (set by l4_thread_schedule, but not yet used?) (5) internal preempter (set by l4_ex_regs, but never used?) (6) l4_thread_switch (7) Preemption RPC (mentioned in the L4 Reference manual, but not implemented, see below) > (2) What differenciate them from scheduling tasks ? > > (3) What is the flow of control, from kernel to elected thread, > at time quantum exhaustion ? Needs to be defined? > (4) What is the role of the L4 internal scheduler, in the presence > of scheduling tasks ? [from another thread:] >> L4 or L4Linux does not use external preempters? >[JW]No, since there is currently no implementation of this concept. There >are some problems with clans&chiefs if you handle 'time slice faults' >(preemption) via ipc. I don't know whether fiasco will provide the >first implementation for external preempters, at least we are thinking >about it. An external preempter has to do at least 3 things: (1) user level scheduling, (2) waits on a kernel side IPC indicating time slice expiration, (3) communication with connected threads (i) inserting/deleting of threads in the user level queues (ii) additional support, time slice and priority changes, etc.. Is there a way to emulate the time slice expiration IPC? The following way may work: As noted in L4 User Manual the External Preempter runs with a higher priority than all other tasks which are scheduled by this external preempter. That means that the external preempter is always scheduled before any other task under control of this external preempter. So the external preempter is able to calculate the time consumed by a thread before the preempter calls l4_thread_switch to switch to the next task. This calculation can emulate the information given by a time slice expiration fault. Further questions are: Who is invoking an external preempter? (rmgr?) Where gets the preempter memory, needed by dynamical sized queues? Does the function ::new() work inside a L4 task, or what is to do to bring ::new() in operation? So far my questions. Regards and a happy new year Harald Fritzsche

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l4-hackers January 1999