l4-hackers February 2006

l4-hackers@os.inf.tu-dresden.de

15 participants
9 discussions

Lovelace Web-Site
by Frederic BOYER 30 Mar '06

30 Mar '06

By the way, Lovelace has now a little web-site (I've just began to do it) and there is a mailing list. Please visit The Lovelace web-site. http://lovelace.rochebrune.org Regards, Frédéric. "This message, including any attachments may contain confidential and privileged material; it is intended only for the person to whom it is addressed. Its contents do not constitute a commitment by Credit Agricole Cheuvreux except where provided for in a written agreement. Credit Agricole Cheuvreux … [View More]

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Re: PowerPC interrupt setup
by Kay-Uwe.Genz 03 Mar '06

03 Mar '06

Hi Joshua, hi @ all, I start this year with first experiments in implementation of an kernel (based on L4.X2) on PowerPC, mostly to learn more about PowerPC/HW and design philosophies. So I read your posting with attention and have some questions ... and hope your answers would made it easier for my to understand. You recommend "enabling virtual addressing immediatly". Did I understand it right, that you use virtual memory in kernel mode? Is this only for protection or means this, … [View More]the kernel memory is vitual? There are other kernels using virtual memory in kernel mode? My design doesn't have a kernel section in the tasks address space (on 32 bit machines a task is 4GB). I agonise to solve some of the problems with this design. In the case StringItems used to send Msg's from one space to another (means copy the information in the kernel) the message buffer on both sides can scattered and located across page bounderies. Handling this seems easier if the kernel has the same view to memory and pionters to memory regions (buffers) but this destroy my approach of lockfreeness, because the String Buffers in different tasks can by overlap or locate at the same virtual adress. (The sendphase of StringItems should by interruptable and at any time it should by possible to handle as much as possible StrinItem sends in the same time.) Handling this in kernel with the view of real memory avoid overlapping buffer regions from different threads. Do you see the issue like I and is there a solution I didn't see? As I see on the homepage, the kernel runs on a G3 (aka PPC750). So you use the normal hardware table search? Thanks for helping. Regards Kay-Uwe. Am 07.02.2006 um 17:35 schrieb Joshua LeVasseur: > > The PowerPC jumps to predefined code locations when delivering > interrupts and traps, starting at 0x100 (with virtual addressing > disabled). You only need to install code at those locations; > PowerPC has no interrupt descriptors. I recommend enabling virtual > addressing immediately, even while handling page faults; I've seen > other kernels implement excessive logic in assembler, executing in > physical mode; that isn't necessary. I enable virtual addressing > within 19 or so instructions. > > Maybe try volume 3 here: > http://www-128.ibm.com/developerworks/eserver/articles/archguide.html > I've never read those documents; I used the 603 architecture manual > when porting L4Ka::Pistachio. > > Consider reading about how I made my L4Ka::Pistachio PowerPC > implementation frigging fast: > http://l4ka.org/projects/pistachio/powerpc/ppc.pdf > It covers: > - Fast system calls (without wasting a register for a system call > number, unlike all other kernels out there that I've seen) > - Fast address space ID management (the way ASIDs were meant to be > managed on the PowerPC, and again, the other kernels out there are > doing it wrong) > - Fast page hash management. Most kernels perform O(n) searches > through the page hash when manually locating an entry. I instead > perform O(1) lookups. > > I recommend that you avoid looking at open source kernels for > guidance. They don't push the limits of PowerPC. > > -Josh > > > > On Feb 7, 2006, at 16:18, Matthias Lange wrote: > >> Hi, >> >> I am stuck with porting the Fiasco microkernel to PowerPC. I can't >> find any clear documentation about how to setup a interrupt >> description table. So, these are my questions: >> >> 1. How is an interrupt descriptor formed on PowerPC? How does it >> look? >> 2. Where (in memory) do I need to store these descriptors? >> >> The IBM PowerPC Programming Manual gives me a good overview but no >> information on how to implement it. Can someone please point me to >> some meaningful documentation? >> >> Regards, >> >> Matthias. >> > > > [View Less]

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trying to launch a server
by Xavier Grave 28 Feb '06

28 Feb '06

Hi all, Always playing with an OS implementation in Ada, I would like to launch a task in an new address space. I have read the example from l4uman-x2.pdf but threse is still some questions for me : - I need to send the task an instruction pointer and stack pointer but in which address space ? - does l4 translate it for me ? - I got a start address (I fink hardware address) from boot info for the server I want to launch does this pointer need translation ? Thanks in advance for any answer (… [View More]

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Question about UTCB
by Jonathan S. Shapiro 24 Feb '06

24 Feb '06

This is a naive, simple question -- I looked in the reference manual and the answer did not jump out at me. When a process is preempted, where are its registers stored? Are the stored in the UTCB, or are they stored in some data structure that is only accessible to the kernel? Thanks shap

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are there any more detailed document?
by Liu Jian 17 Feb '06

17 Feb '06

Hi all, I find the course "Microkernel Construction" is a good choice to newmen to Fiasco. If there was any detailed document about the design of Fiasco with it, it will be wonderful. If you know such documents, pls let me known and I will appreciate your direction. Moreover, I plan to give a series of seminars about Fiasco in our group based on the course documents. I also wonder how the teachers at Dresden to carry out the curse. cheers:) Liu Jian

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PowerPC interrupt setup
by Matthias Lange 08 Feb '06

08 Feb '06

Hi, I am stuck with porting the Fiasco microkernel to PowerPC. I can't find any clear documentation about how to setup a interrupt description table. So, these are my questions: 1. How is an interrupt descriptor formed on PowerPC? How does it look? 2. Where (in memory) do I need to store these descriptors? The IBM PowerPC Programming Manual gives me a good overview but no information on how to implement it. Can someone please point me to some meaningful documentation? Regards, Matthias.

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Ore on Intel Pro/1000
by Michael Scheibel 07 Feb '06

07 Feb '06

Hello list, I am running Ore on native HW and Intel(R) PRO/1000 Network Connection. Ore seems to recognize the network card correctly but quits when I try to setup eth0. L4Linux error message: eth0: Overwriting IRQ type for IRQ 0 with l4ore type! eth0: request_irq(0, ...) failed. Any hint highly appreciated. Regards, Michael -- Sirrix AG security technologies - http://www.sirrix-ag.de Michael Scheibel eMail: m.scheibel(a)sirrix.com Tel +49(234) 610 071-124 Public key on demand … [View More]

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Fiasco and L4Linux for ARM926 (Nokia770)
by Delitsyn Igor 07 Feb '06

07 Feb '06

Hi fellow L4 hackers, We´d like to port Fiasco kernal to ARM926 processor, which is used in Nokia770 internet tablet device. Later we plan to run L4Linux on the device as well. We would really appreciate any recommendations from you on how to proceed and links to necessary resources, especially from those who made the porting to SA1110 and PXA. Best regards, Igor

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Ada L4
by Frederic BOYER 03 Feb '06

03 Feb '06

Hi L4'er ... We have began to rewrite a L4 lib with Ada and by now : - We have all L4 types (threads, ...) - We make system calls - We Allocate memory - We have a minimal support exceptions. Currently we are working on tasks. We'd like to get a little help from L4 teams in order to make our OS design. If some peoples in the L4 team have some experience with L4, please contact me. Regards, Frédéric. "This message, including any attachments may contain confidential and privileged … [View More]

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l4-hackers February 2006