l4-hackers March 2013

l4-hackers@os.inf.tu-dresden.de

17 participants
15 discussions

Re: memory problem about s5pv210 porting
by meng-qy 05 Mar '13

05 Mar '13

Hi,Adam, The problem has been solved, thank you for your supports! Indeed, that fault is caused by cache. In file "pagetable-arch", the code only flush dcache and do not flush icache which leads to this unstable phenomenon. Now, the system seem to ok after I adding it. Steven Meng On 2013年03月01日 19:00, l4-hackers-request(a)os.inf.tu-dresden.de wrote: > On Thu Feb 28, 2013 at 21:33:53 +0800, meng-qy wrote: >> > Thank you for your suggestion! Following your guidance, I log the PF info when system dead like this: >> > >> > test 1: >> > pf: 000a pfa=2016a8f8 ip=2016a8f8 (r-) spc=0xf12e475c 144 >> > pf: 000a pfa=2016a8f8 ip=2016a8f8 (r-) spc=0xf12e475c 143 >> > pf: 000a pfa=2016a8f8 ip=2016a8f8 (r-) spc=0xf12e475c 142 >> > pf: 000a pfa=2016a8f8 ip=2016a8f8 (r-) spc=0xf12e475c 141 >> > pf: 000a pfa=2016a8f8 ip=2016a8f8 (r-) spc=0xf12e475c 140 >> > test 2: >> > pf: 000a pfa=20144128 ip=20144128 (r-) spc=0xf12e475c 105 >> > pf: 000a pfa=20144128 ip=20144128 (r-) spc=0xf12e475c 104 >> > pf: 000a pfa=20144128 ip=20144128 (r-) spc=0xf12e475c 103 >> > pf: 000a pfa=20144128 ip=20144128 (r-) spc=0xf12e475c 102 >> > test 3: >> > pf: 000a pfa=2016a8f8 ip=2016a8f8 (r-) spc=0xf12e475c 116 >> > pf: 000a pfa=2016a8f8 ip=2016a8f8 (r-) spc=0xf12e475c 115 >> > pf: 000a pfa=2016a8f8 ip=2016a8f8 (r-) spc=0xf12e475c 114 >> > pf: 000a pfa=2016a8f8 ip=2016a8f8 (r-) spc=0xf12e475c 113 >> > pf: 000a pfa=2016a8f8 ip=2016a8f8 (r-) spc=0xf12e475c 112 >> > >> > What is spc? pc or sp ? I objdump the image, and did not found that address. > pc is the program counter, sp is the stack pointer, spc is a kernel > internal data structure (Space). So this is a code pagefault, likely in > the roottask/moe. > >> > However, we can't get more info in dump file because the file didn't include any symbol table(Can we >> > dump the symbol table by adding some compile option? ). > Use fiasco.image file for the kernel. > >> > At last, different from other chip, we found that address >> > e0000000-fb000000 in s5pv210 is some important register, and the >> > kernel seem to map that address, it doesn't matter? > What you describe are physical addresses, the kernel uses virtual ones, > i.e. the virtual address does not point to the physical address. So yes, > it does not matter. > > > > > Adam > -- Adam adam(a)os.inf.tu-dresden.de Lackorzynski > http://os.inf.tu-dresden.de/~adam/ --------------------------------------------------------------------------------------------------- Confidentiality Notice: The information contained in this e-mail and any accompanying attachment(s) is intended only for the use of the intended recipient and may be confidential and/or privileged of Neusoft Corporation, its subsidiaries and/or its affiliates. If any reader of this communication is not the intended recipient, unauthorized use, forwarding, printing, storing, disclosure or copying is strictly prohibited, and may be unlawful.If you have received this communication in error,please immediately notify the sender by return e-mail, and delete the original message and all copies from your system. Thank you. ---------------------------------------------------------------------------------------------------

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Genode OS Framework version 13.02 released
by Sebastian Sumpf 03 Mar '13

03 Mar '13

We are pleased to announce the release of Genode version 13.02. The most prominent features are the improved handling of dynamic workloads on the NOVA hypervisor, IOMMU support as well as the integration of Markus Pateymüller's work on the Vancouver VMM. Fiasco.OC has been updated to the most recent version and there are new platforms available for our custom kernel. The full story can be explored in the release notes: http://genode.org/documentation/release-notes/13.02 Release-notes summary: - DMA protection via IOMMU (NOVA/x86) - Full virtualization via the Vancouver VMM (NOVA/x86) - Redesigned audio-output support for low latency - Base API and OS infrastructure - New fault-detection facility - New mechanism for file-system notifications - New terminal multiplexer - Device drivers - ACPI support for 64-bit machines - New OMAP4 UART driver - USB support for Samsung Exynos 5250 - Base platforms - Custom kernel platform with added support for Samsung Exynos 5250 and Freescale i.MX53 - NOVA kernel improved for highly dynamic workloads - Fiasco.OC kernel forked, Exynos-5250 support added - Improved memory management on Linux Enjoy, Sebastian -- Sebastian Sumpf Genode Labs http://www.genode-labs.com · http://genode.org Genode Labs GmbH · Amtsgericht Dresden · HRB 28424 · Sitz Dresden Geschäftsführer: Dr.-Ing. Norman Feske, Christian Helmuth

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Re: Fiasco.OC performance issues
by Sebastian Sumpf 03 Mar '13

03 Mar '13

On 01/29/2013 12:09 AM, Adam Lackorzynski wrote: > On Fri Jan 25, 2013 at 00:00:26 +0100, Sebastian Sumpf wrote: >> On 01/17/2013 11:31 PM, Adam Lackorzynski wrote: >>> On Thu Jan 17, 2013 at 17:03:36 +0100, Sebastian Sumpf wrote: >>>> I recently upgraded Fiasco.OC to SVN revision 42 and experience some >>>> pretty severe performance degradation compared to revision 40 on the >>>> Pandaboard (SMP). It seems that 'simga0' and the root task stall for 5 >>>> to 10 seconds during boot up. I tracked the issue down to be caused by >>>> the initial mapping operations, especially our root task maps all the >>>> available memory during bootstrap. Within the kernel the >>>> 'Context::xcpu_tlb_flush' is called for each mapping. The function sends >>>> an IPI (to CPU1 which is idle) and then waits for an IPI in order to >>>> signal the end of the operation. The whole operation seems to have >>>> gotten slower compared to revision 40, but I could not find many >>>> differences in the IPI-handling code. Do you have any ideas or >>>> suggestions what could cause the delay (maybe scheduling changes) and >>>> how to fix it? >>> >>> I noticed a similar/same thing but hadn't time to investigate yet. >> >> Okay, I just wanted to make sure that the problem is not at our side nor >> at our usage pattern. >> Another thing I wonder is: Since you now have second level cache support >> for the PandaBoard, how do I map DMA memory to a client? The problem >> seems to be that sigma0 maps all memory as cached. So what we have been >> trying to do is this: When someone requests DMA memory we map the page >> as uncached and then call 'l4_cache_dma_coherent' afterwards. This >> doesn't seem to work out well for our drivers. The thing I think I could >> gather is that memory that is mapped cached (sigma0, roottask) and >> uncached (client) at the same time has an undefined behavior (I might be >> wrong here) on ARM. So, what is the protocol to implement this on >> Fiasco.OC/L4RE setups? > > Indeed, having memory with different attributes must be avoided. > But it's also about accessing that memory. So for example for sigma0 > this isn't a problem because sigma0 does not touch the memory itself. > Is your roottask accessing the memory, i.e. pulling it into caches? Yes this is the problem we're trying to solve. We don't have a notice of normal RAM and DMA pools within our roottask (if we had this, the question of how to dimension DMA pools would arise, also this seems to be an ARM only issue). So here is what we did with L1 caches enabled only: Acquire the memory in roottask, map it to the client as non-cacheable, zero out the memory (as it might have been previously used as normal RAM and for security reasons), clean and invalidate the data-cache. With the L2-cache enabled on PandaBoard, I tried to use the 'l4_cache_dma_coherent' function to accomplish the same behavior, which worked out well for the L1-case ... but it didn't. So, what am I doing wrong here, or isn't this supported anyways? Thanks a lot, Sebstian

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How to start a program in a application ?
by Jason.han 02 Mar '13

02 Mar '13

Hi all, I want to start a program in my application ,(e.g task A--->start task B) I can't get enough information in latest source version , so I wonder if some know whether there is some system call like fork() or APIs to do this. Please give me some suggestion ,and example it preferred . --------------------------------------------------------------------------------------------------- Confidentiality Notice: The information contained in this e-mail and any accompanying attachment(s) is intended only for the use of the intended recipient and may be confidential and/or privileged of Neusoft Corporation, its subsidiaries and/or its affiliates. If any reader of this communication is not the intended recipient, unauthorized use, forwarding, printing, storing, disclosure or copying is strictly prohibited, and may be unlawful.If you have received this communication in error,please immediately notify the sender by return e-mail, and delete the original message and all copies from your system. Thank you. ---------------------------------------------------------------------------------------------------

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RE: Re: [ARM11] Question for the ARM 11 GPIO MAPPING
by Jason.han 02 Mar '13

02 Mar '13

Dear Adam : Thank you very much ! Now I have understand the IO MAPPING rules . All IO address mapping is only recognized by first 5 bits ,the last three bit is no mean for address(only for flags) . I mapping the S3C6410 GPIO ,Video-control ,Sfr once again . Now i can make the LCD bright and run the spectrum in real hardware . Thanks . Best regards ~~ ------------------------------ Message: 2 Date: Wed, 27 Feb 2013 22:13:47 +0100 From: Adam Lackorzynski <adam(a)os.inf.tu-dresden.de> To: l4-hackers(a)os.inf.tu-dresden.de Subject: Re: [ARM11] Question for the ARM 11 GPIO MAPPING Message-ID: <20130227211347.GA6841(a)os.inf.tu-dresden.de> Content-Type: text/plain; charset=iso-8859-1 Hi, On Tue Feb 26, 2013 at 20:10:15 +0800, Jason.han wrote: >> Now I have GPIO Mapping problems happened when >> run the L4re in Arm 11 (6410 ). >> >> .devs ==> Res.mmio(0x7f008100, 0x7f00813f); >> .lcd.c ==>l4io_request_iomem(0x7f008100, 0x03f, >> L4IO_MEM_NONCACHED, &lcd_gpio_virt_base); >> >> when >> "l4_mem_write(lcd_gpio_virt_base+0x00,L4_MEM_WIDTH_4BYTE,0xaaaaaaaa); >> download in real-hw board : the core will died as it : >> >> Ned: loading file: 'rom/arm-rv-lcd.cfg' >> >> hello | Hello World! >> IO | Dev_factory: register factory for N2Hw6DeviceE >> IO | GTF: register factory for 7Pci_dev >> IO | GTF: register factory for N2Hw12Msi_resourceE >> IO | Dev_factory: register factory for N2Hw11Gpio_deviceE >> IO | Io service >> IO | Ready. Waiting for request. >> fbdrv | Using LCD driver: S3C6410 >> fbdrv | lcd_control_virt_base is 0x3000 >> fbdrv | lcd_gpio_virt_base is 0x4000 >> fbdrv | Video memory is at virtual 0x5000 (size: 0x3fc00 Bytes) >> fbdrv | Physical video memory is at 0x50394000 ==>core died >> >> after delete it and only use l4_mem_read , value always is >> >> IO | Ready. Waiting for request. >> >> fbdrv | Using LCD driver: S3C6410 >> fbdrv | lcd_control_virt_base is 0x3000 >> fbdrv | lcd_gpio_virt_base is 0x4000 >> fbdrv | Video memory is at virtual 0x5000 (size: 0x3fc00 Bytes) >> fbdrv | Physical video memory is at 0x50395000 >> fbdrv | 0 value is 0x220022 ==> core run is ok. >> >> In the range of the GPIO ,whatever I defined , the >> lcd_gpio_virt_base + offset (value 0) is always 0x220022 ,can't >> be written . >> the lcd_gpio_virt_base + offset (value 0x04) is always 0x23 ,can >> be written ,but value never be changed . >> From Offset (value 0x08) is normal . why only GPIO like this ,I >> write some time and control -register always OK. >> >> Do you know Why , Can you give me some advices ? Thank you . >> >> I also try to .devs ==> Res.mmio(0x7f008000, 0x7f00813f); >> .lcd.c ==>l4io_request_iomem(0x7f008000, >> 0x03f, L4IO_MEM_NONCACHED, &lcd_gpio_virt_base); >> when >> "l4_mem_write(lcd_gpio_virt_base+0x100,L4_MEM_WIDTH_4BYTE,0xaaaaaaaa); >> The offset 0x00 ,and 0x04 same problem ,but now I can write >> 0xaaaaaaaa for this IO port, even though working not well . > What I notice is that you want to have 0x7f008100, however, mappings are > page granular, i.e. lower 3 digits are 0. The output says the virt_base > is 0x4000, so you probably want to access 0x4100. Maybe the device at > offset 0 is behaving like what you're seeing. > > > > > Adam --------------------------------------------------------------------------------------------------- Confidentiality Notice: The information contained in this e-mail and any accompanying attachment(s) is intended only for the use of the intended recipient and may be confidential and/or privileged of Neusoft Corporation, its subsidiaries and/or its affiliates. If any reader of this communication is not the intended recipient, unauthorized use, forwarding, printing, storing, disclosure or copying is strictly prohibited, and may be unlawful.If you have received this communication in error,please immediately notify the sender by return e-mail, and delete the original message and all copies from your system. Thank you. ---------------------------------------------------------------------------------------------------

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l4-hackers March 2013