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Assertion failure error in kernel vgic interrupt processing
by nico 10 Apr '18

10 Apr '18

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Entrypoint for user-space syscall instruction
by Zihan Yang 26 Mar '18

26 Mar '18

Hi, I'm trying to figure out the entry for 'syscall' in Fiasco, I already know that Fiasco will set MSR_STAR, MSR_LSTAR and MSR_CSTAR in Cpu::setup_sysenter. However, things don't seem right when I run a simple program of my own, which is compiled statically outside in Ubuntu with gcc 5.4.0. This program directly issues a single 'syscall' instruction (instead of the syscall() function), which is equivalent to getpid(). Here is the program, which is compiled with gcc -static -o syscall_single -O2 -std=gnu99 syscall_single.c -------------------- BEGIN --------------------- //syscall_single.c //gcc -static -o syscall_single -O2 -std=gnu99 syscall_single.c #include <stdio.h> void printres(unsigned long res) { printf("Done, id = %d\n", res); } int main() { asm volatile( "mov $39, %%rax\n" "syscall\n" "mov %%rax, %%rdi\n" "call printres" : : : "cc" ); return 0; } --------------------- END ------------------------ Since Fiasco has specified MSR_LSTAR, I expect every normal system call to goto the 'entry_sys_fast_ipc_c' in src/kern/ia32/64/entry-native.S, therefore I add such line at the beginning of entry_sys_fast_ipc_c -------------------- BEGIN --------------------- .extern unsigned long test_rax; entry_sys_fast_ipc_c: movq %rax, test_rax //mov rax to the global variable test_rax --------------------- END ------------------------ And I print this variable in 'sys_ipc_wrapper'. Now strange things happen, when I type './syscall_single' in the shell, test_rax is never 39 at any time! But yet it can get the right result, and there is output in 'dispatch_system_call' in l4linux side(manually added by me). My questions are (1) What is the entrypoint and actual path if a user program directly issues a syscall instruction? (2) I find dispatch_system_call judges whether there is a system call based on the 'trap_nr' field of thread_struct, does this mean it is implemented through exception? Thanks.

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Ben NanoNote patches (MIPS/Ingenic JZ4720) and memory mapping issues
by Paul Boddie 17 Mar '18

17 Mar '18

Hello, Accompanying my patches for the MIPS Creator CI20 (Ingenic JZ4780), I have some patches that get Fiasco.OC booting on the Ben NanoNote (Ingenic JZ4720). Currently, I can get a task running that shows some data on the screen. More details about the Ben NanoNote can be found here: http://en.qi-hardware.com/wiki/Ben_NanoNote (It is a "palmtop" device from around 2010 that was made in fairly limited quantities but unfortunately didn't get the attention it deserved that might have seen follow-on models, and many more units, being made.) Unfortunately, the data I display on the screen isn't aligned properly. This isn't a fundamental problem since I was happily using the screen to emit bit patterns in order to debug the kernel while working to bring it up on the hardware. However, now, in my example task, I see what would appear to be a 9-pixel misalignment with the screen. Something like this, each digit being a pixel of a certain colour, with groups of ten sharing the same colour: 122222222223333333333...111111111 Although I suspect that this is some kind of peripheral initialisation issue, none of the device registers are any different from before, and I can even neglect to initialise most of them, keeping the configuration from the bootloader, and still see the problem. The registers I do have to change are the ones that tell the LCD peripheral where the framebuffer is, but I can check that the values I use are consistent with where I am storing screen data. So it makes sense to me to check whether there might be something related to L4Re or Fiasco.OC (and my modifications, of course) that could be causing this. In my task, I do the following: l4re_ma_alloc_align(fb_size, fbmem, L4RE_MA_CONTINUOUS | L4RE_MA_PINNED, 6) Here, the documentation indicates that the alignment will be 2**6 or 64 bytes, although it will in practice be page-aligned and thus 4096 bytes in my case. This, upon success, is then followed by this: l4re_rm_attach(&fb_vaddr, fb_size,L4RE_RM_SEARCH_ADDR | L4RE_RM_EAGER_MAP, fbmem, 0, L4_PAGESHIFT) And upon success, I obtain the physical address for the region: l4re_ds_phys(fbmem, 0, &fb_paddr, &fb_size_out) Both the virtual and physical addresses seem to be page-aligned. From my limited knowledge of the hardware, I cannot envisage a situation where writes to the physical memory would be offset, let alone wrapped in the way described above. But I suppose I could easily be unaware of other things that might be happening, and so it seems worthwhile to ask around. By the way, my patches are here: http://www.boddie.org.uk/paul/L4Re-Fiasco.OC.html I would certainly appreciate hearing any ideas about things I might have overlooked. Thanks, Paul

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I got an issue, when testing command like this :qemu–system–aarch64 -kernel uimage -smp 2...
by Jiang qihong 14 Mar '18

14 Mar '18

The whole command , qemu–system–aarch64 -kernel uimage -M vexpress -a15 -cpu cortex-a57 -smp 2 -m256 --nographic The issue is that when running into shell, i didn't find two cpus. The parameter "-smp 2",didn't work. Does qemu support arch arm -v8 when using the parameter(-smp)? From jqh mobile phone.

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How to show call path in backtrace with jdb?
by Zihan Yang 14 Mar '18

14 Mar '18

Hi all, I'm trying to debug L4Linux using jdb in Fiasco. I have added a breakpoint in a function(e.g, syscall_exit), and it did hit into jdb when I run. However, when I type 'bt' in jdb, it only prints the values in the stack, or worse, it sometimes couldn't print the stack. I have tried enabling L4_DEBUG_REGISTER_NAMES and CONFIG_FRAME_POINTER in L4Linux, and uncheck 'config without frame pointer' and 'generate inline code' options in Fiasco, but still it doesn't work. QEMU could be an option, but qemu debugs the whole system while I just want to focus on the L4Linux itself because I just want to figure out the call path of ret_from_fork and how does L4Linux stop the user dispatch loop, etc. Is there any way to show the the call path in jdb to assist the debugging work? By way, is there any doc describing the call path from fiasco to L4Linux, I know it is implemented with sysretq or iretq, but where is the entrypoint in L4Linux? For example, when I type 'ls /bin' in shell, it would finally go into L4Linux's function 'syscall_exit()', but how can I find the call path between them? If I can figure it out, maybe I just don't need to debug anymore. Thanks

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Is the L4Linux running as a Fiasco.OC server?
by Zeyu Mi 09 Mar '18

09 Mar '18

Hi all, I am studying the implementation of the Fiasco.OC and the L4Linux. I have searched on the Internet and many papers and documents record that L4Linux runs as an L4 server and any L4Linux user process is a new task, which has a new page table different from that of an L4Linux server. However, the experiment result seems to conflict with those documents. When I started a new program in the L4Linux shell and used "lp" command (show present list) in JDB, I noticed that there was one thread having "vcpu" state. But the resulted list did not contain any new thread or task which is related to the new program. I am very confused and wondering whether or not the implementation recorded in those papers or documents are wrong or obsolete? The experiment is based on "l4re-snapshot-2016082114". Thanks in advance for any explanation. -- Best Regards Zeyu Mi

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Activating the sigma0 thread in the Fiasco kernel
by Paul Boddie 08 Mar '18

08 Mar '18

Hello, I've been trying to coerce L4Re and Fiasco.OC to work with the Ben NanoNote, which is related to the MIPS Creator CI20 that is (mostly - see earlier discussions) supported by this software. There are a few challenges involved, such as avoiding MIPS32r2 instructions that the NanoNote's SoC doesn't support (JZ4740 in the NanoNote versus JZ4780 in the CI20), and positioning things appropriately to avoid upsetting the installed bootloader. Since I last posted anything about this, I've managed to get Fiasco to go about its bootstrapping business, proceeding from the bootstrap package, entering the kernel, running kernel_main, doing various initialisation tasks, enabling interrupts, and ending up in the init_workload method where a sigma0 thread and a boot thread are created and activated. It is at this point that I seem to have encountered a particularly stubborn problem: how to get the sigma0 thread to activate and return control to init_workload for the boot thread to be activated, then going on to finish what little remains of the bootstrapping process. Strangely, the boot thread has no difficulty in being activated and returning control if I put it first in the sequence, but sigma0 seems to cause something different to happen. Now, for this activation, it seems that the real action begins in Context::switch_cpu, where an exchange of stack pointers occurs and a branch is made to the Context::switchin_context method, with the old context presumably being made to resume after the branchpoint. As far as I can tell, both threads manage to set this up correctly. I see that the new context then causes Thread::user_invoke to be called, with execution proceeding via the ret_from_user_invoke routine and ultimately into the user task. Looking at the address to which the CPU will "return" to in user mode, all seems reasonable and consistent with the configuration of sigma0. However, one thing that baffles me somewhat is the way that interrupts are disabled in Thread::user_invoke. Given that the CPU ends up in the task in user mode, it would surely need some kind of exception or interrupt for the kernel to be re-entered, yet I don't see any operation that re-enables interrupts anywhere. Maybe this is the cause of my problem, but I don't understand how sigma0 would be different from anything else. I have needed to change some CPU-level operations to adapt the code to the earlier microarchitecture revision, but I don't think I've made any obvious mistakes, and I have seemingly figured out how to describe the interrupt system because for a while I couldn't get past the Delay::init invocation in the bootstrap process which relies on interrupts working. (Some comments in the code would have helped me guess what numbers to use in certain invocations.) Does anyone have any thoughts or guidance about what I should be looking at? Thanks in advance and sorry for the wall of text! Paul

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Fiasco.OC development version available on github
by Matthias Lange 22 Feb '18

22 Feb '18

Hi, Kernkonzept proudly announces the availability of a development version of the Fiasco.OC microkernel on github [1]. It features a detailed history and will be updated regularly. Those interested in exploring the latest changes can amend the latest L4Re snapshot release (see [2]) with this development version. We plan to release development versions of the build system and selected userspace components in the weeks ahead. So, let us know what you think. Cheers, Matthias. [1] https://github.com/kernkonzept/fiasco [2] https://l4re.org/download.html -- Matthias Lange, matthias.lange(a)kernkonzept.com, +49-351-41 888 614 Kernkonzept GmbH. Sitz: Dresden. Amtsgericht Dresden, HRB 31129. Geschäftsführer: Dr.-Ing. Michael Hohmuth

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L4Linux performance vs hardware virtualization
by Bob Liu 12 Feb '18

12 Feb '18

Hi Folks, L4Linux.org mentioned: "Compared to monolithic Linux, there is a small performance tradeoff because of the µ-kernel architecture. However, the initial L4Linux has been somewhat optimized, and on L4/x86 it has a very acceptable slowdown of less than 4 % for any relevant load. " Any place can find more detail about the test? And I'm very curious the L4Linux performance vs "using hardware virtualization on top of L4", have you made any comparison before? -- Thank you! Bob

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Microkernel and alumni meetup
by Matthias Lange 11 Feb '18

11 Feb '18

Dear friends of the microkernel, it's about time for another microkernel and alumni meetup to catch up on all the developments of the last 6 months. Let's meet for a beer or two. To find a date that fits the most people please visit https://dudle.inf.tu-dresden.de/Microkernel_Meetup/ and add your preferred day. Regards, Matthias. -- Matthias Lange, matthias.lange(a)kernkonzept.com, +49-351-41 888 614 Kernkonzept GmbH. Sitz: Dresden. Amtsgericht Dresden, HRB 31129. Geschäftsführer: Dr.-Ing. Michael Hohmuth

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MIPS Creator CI20 patches (again)
by Paul Boddie 06 Feb '18

06 Feb '18

Hello, I recently looked at the collection of patches accumulated when trying to get the CI20 support to a functioning state, and I think I've brought them up to date with the latest upstream repository version (r75). In doing so, I've also tried to break them up into distinct parcels of functionality so that the less interesting or less relevant patches can be ignored. A page describing the patches can be found here: http://www.boddie.org.uk/paul/L4Re-Fiasco.OC.html None of these patches have changed since previous discussions on this topic. The rdhwr instruction support I needed to add, for instance, is still done in MIPS assembly language, fitting in with existing support for another variant of that instruction. Anyway, I thought it might be useful to put them somewhere with a description for future reference. I've yet to get round to looking seriously at L4Re on the CI20 again and it isn't likely to happen now before the end of the year. Paul

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Get instruction opcode + operands for page fault
by Josef Stark 04 Feb '18

04 Feb '18

Hi all, when a page fault occurs, does the Instruction Register contain the actual instruction that caused the fault or the previous instruction? In the former case, how can I access it? I need the opcode + the operands (like source/target registers). I already have the memory address that the instruction tried to access. I'm on ARM A9, so only load/store instructions can cause a page fault. I know that I could also look at the address where my IP is pointing to and get the instruction from there, but I'm wondering which way would be easier/better. Cheers, Josef

2 1

Build problems on i386 (Fiasco-OC.UX)
by Paul Boddie 30 Jan '18

30 Jan '18

Hello, More awkward news from Debian on i386! I was looking to build the "Linux Usermode Platform" variant of Fiasco-OC on i386 (well, Pentium 4) and encountered a couple of issues. Firstly, "struct ucontext" is mentioned in src/kern/ux/usermode.cpp but has been deprecated in favour of "ucontext_t". There are some User Mode Linux reports about this: https://lkml.org/lkml/2017/11/15/159 https://lkml.org/lkml/2018/1/25/522 A search-and-replace involving the two terms fixes the compilation error that otherwise occurs. Secondly, linking of the kernel fails due to symbol conflicts between the minilibc functionality and glibc: /usr/lib/gcc/i686-linux-gnu/6/../../../i386-linux-gnu/libc.a(memcmp.o): In function `memcmp': (.text+0x0): multiple definition of `memcmp' libc.a(memcmp.o):/home/paulb/L4/UX-75/src/kernel/fiasco/src/lib/minilibc/memcmp.c:7: first defined here collect2: error: ld returned 1 exit status /home/paulb/L4/UX-75/src/kernel/fiasco/src/kern/ux/Makerules.KERNEL:35: recipe for target 'fiasco.debug' failed So, not knowing how best to deal with this, I relied on the --allow-multiple- definition linker option: https://gcc.gnu.org/ml/gcc-help/2009-09/msg00108.html I doubt that this is the right way to deal with it. Maybe GCC 6.4 (Debian 6.4.0-12) introduced some behaviour that is not compatible with the way this linking is being done. Both of the above issues are present in repository versions 74, 75 and 76 at the very least. Certainly, the first issue is not likely to be absent in earlier versions. Paul P.S. I have also been experiencing a build problem with L4Re on i386, but this will be described in another message.

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Build problems on i386 (L4Re)
by Paul Boddie 30 Jan '18

30 Jan '18

As promised, my other error report... With Fiasco-OC built, I concentrated on building L4Re for i386, but this led to me encountering this rather frustrating error: [l4util] ==> Linking to shared libl4util.so /home/paulb/L4/UX-75/src/l4/mk/lib.mk:139: recipe for target 'libl4util.so' failed make[4]: *** [libl4util.so] Segmentation fault make[4]: *** Deleting file 'libl4util.so' ../../../../../mk/binary.inc:164: recipe for target '/home/paulb/L4/UX-75/src/l4/mybuild/pkg/l4re-core/l4util/lib/src/OBJ-x86_gen- l4f' failed This issue is present in repository versions 72 through 76. Again, I'm testing this with GCC 6.4 (Debian 6.4.0-12). I've not seen this at all when cross- compiling, either with the Debian or with Buildroot compilers. Paul

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OS Engineers Wanted!
by Gernot Heiser 30 Jan '18

30 Jan '18

[Apology for the shameless ad, but might be of interest to some] Would you like to get paid for making the world more secure with seL4? I'm in charge of directing OS development for the newly-founded company Hensoldt Cyber. We will develop an integrated, highly-secure hardware-software solution, combined with secure production, aimed at changing the game in securing real-world embedded/cyber-physical systems. Needless to say, there will be close collaboration with the Data61 Trustworthy Systems team. We're now hiring engineers who will help us getting there. Specifically, we're looking for strongly-motivated people with practical experience in OS development, although there is flexibility with the degree of experience. Actual experience with L4 microkernels would be awesome. Place of work will be Munich (no remote work possible, sorry). You'll have to be prepared to obtain a German government security clearance (German citizenship is not a requirement for this). Interested? Please send me your CV. Gernot

1 0

Access ARM Data Fault Address Register (System Control Register) in Fiasco.OC
by Stark, Josef 26 Jan '18

26 Jan '18

Hey, in Fiasco.OC we have a function inside src/kernel/foc/l4/pkg/l4sys/include/thread.h > L4_INLINE l4_msgtag_t > l4_thread_ex_regs_ret(l4_cap_idx_t thread, l4_addr_t *ip, l4_addr_t *sp, > l4_umword_t *flags) L4_NOTHROW; which allows us for a given thread (capability ID) to read its general purpose registers, SP and IP. Is there a similar function (if not, how could I achieve it) to access the ARM A9 System control registers or, to be more precise, the Data Fault Address Register (DFAR) [1] of a thread? I tried creating a function similar to the above mentioned, but modified the body to do this: > unsigned int v; > asm volatile ("mrc p15, 0, %[v], c6, c0, 0" : [v]"=r"(v) :: ); and then write v back to the caller. But this just made the whole system hang. Any ideas? Thanks in advance! Best regards, Josef [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100511_0401_10_…

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L4/Fiasco kernel debugger (jdb) and step over command
by Valery V. Sedletski 22 Jan '18

22 Jan '18

Hi. I'm trying to debug my program with jdb. (I'm using the old L4/Fiasco / L4Env, not the current Fiasco.OC / L4Re). I enabled the permanent single step mode (with the S+ command) and a permanent show the Thread Control Block (with the t+ command) option. So, I was able to single-step with "g" command. Also, I found "jr" (go until return (ret or iret) is encountered) and "jb" (go until the next branch instruction, like jmp/call/int) commands, but they don't seem to work. When I enter them, I see only a single step to the next instruction. Are these two commands broken? How do I step over a "call"/"int" instruction? Thanks in advance, valery

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Re: Question about vm memory initialization
by nico 11 Jan '18

11 Jan '18

2 2

Workaround to build l4linux for ARM Target
by Leslie Zhai 10 Jan '18

10 Jan '18

Hi l4 hackers, ../arch/l4/arm-mach-l4/l4.c:33:10: fatal error: l4/io/io.h: No such file or directory #include <l4/io/io.h> ^~~~~~~~~~~~ compilation terminated. so I just workaround to `ln -s` manually: build-freescale-imx6/include/l4/io/ ├── io.h -> /data/project/xiangzhai/l4re/l4/pkg/io/libio-io/include/io.h ├── pciids.h -> /data/project/xiangzhai/l4re/l4/pkg/io/io/server/libpciids/include/pciids.h └── types.h -> /data/project/xiangzhai/l4re/l4/pkg/io/libio-io/include/types.h l4re version: svn76 l4linux version: svn57 GNU toolchain: gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11) I think it might be `Makefile` simple issue :) -- Regards, Leslie Zhai - https://reviews.llvm.org/p/xiangzhai/

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Question about vm memory initialization
by nico 10 Jan '18

10 Jan '18

Hi Adam, I started uvmm and found that all ram space allocated to vm are cleared. But I do not need to do that, because uboot has loaded image file to ram, and vm linux would use that image file. Could you tell me where the uvmm did the cleanup? Regards, Nico

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L4Re and Meltdown / Spectre attacks
by Matthias Lange 08 Jan '18

08 Jan '18

Hi, after the dust around the Meltdown and Spectre attacks has settled a bit, you may wonder how Fiasco.OC / L4Re fares with regard to these attacks. Fiasco.OC / L4Re is vulnerable to Meltdown-like attacks because the kernel is mapped into each task. However, the kernel does not map all physical memory but only memory it requires for its own data structures + kernel-user memory required for e.g. UTCBs and vCPU state save areas. Depending on the amount of physical memory and the available page sizes, Fiasco.OC may map it little bit more than that to save TLB entries. That means there can be a slight overlap of user memory that is visible to the kernel. But it is not possible for a thread to read _all_ memory. Because we think that no thread should read information from other threads (pagetables, capability arrays, UTCBs etc.), we plan to change Fiasco.OC to execute in its own address space on Intel CPUs. Against Spectre we do not plan to implement anything right now. We think the attack surface of the kernel is very little (if any) and may be even further reduced with Intel's microcode updates and future compiler/tool mitigations. However, we will observe future discussions and developments and may reassess this in the future. Thank you and regards, Matthias. -- Kernkonzept GmbH. Sitz: Dresden. Amtsgericht Dresden, HRB 31129. Geschäftsführer: Dr.-Ing. Michael Hohmuth

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Fiasco.OC port on Jailhouse
by Muneeswaran Rajendran 19 Dec '17

19 Dec '17

Hi, I trying to understand the porting of fiasco.OC kernel into jailhouse but not able locate the source code of jailhouse porting code for fiasco.OC kernel. Please share the same. I refer this below document to get 'jailhouse/configs/fiasco-demo.c' this file. But i do not find it. https://rtime.felk.cvut.cz/~sojka/students/F3-BP-2016-Baryshnikov-Maxim-bar… Please help me out to find out. Regards, Munees

1 0

exception while running L4linux on raspberry pi 2
by vmc doe 18 Dec '17

18 Dec '17

Hi Adam/l4-hackers, I tried to build l4+l4Re+l4linux for raspberry pi 2. The build was successful, but when I tried to run this in qemu I am getting the following error. Could you pls help me to fix this error? I am new to L4 and L4Re and would like to try out some virtualization options with L4 Microkernel. Could you pls suggest some initial modules or portions where I can start with. Regards vmc L4 Bootstrapper Build: #3 Mon Dec 11 15:24:01 IST 2017, 4.8.3 20140303 (prerelease) Scanning up to 512 MB RAM, starting at offset 32MB Memory size is 512MB (00000000 - 1fffffff) RAM: 0000000000000000 - 000000001fffffff: 524288kB Total RAM: 512MB Scanning fiasco Scanning sigma0 Scanning moe Moving up to 8 modules behind 1100000 moving module 02 { 1823000-18544df } -> { 1914000-19454df } [201952] moving module 01 { 1811000-1822373 } -> { 1902000-1913373 } [70516] moving module 00 { 1786000-1810e23 } -> { 1877000-1901e23 } [568868] moving module 07 { 1486000-1785fff } -> { 1577000-1876fff } [3145728] moving module 06 { 108c000-148547f } -> { 117d000-157647f } [4166784] moving module 05 { 102a000-108b717 } -> { 111b000-117c717 } [399128] moving module 04 { 1010000-10294a3 } -> { 1101000-111a4a3 } [103588] moving module 03 { 100f000-100f12d } -> { 1100000-110012d } [302] Loading fiasco Loading sigma0 Loading moe find kernel info page... found kernel info page (via ELF) at 2000 Regions of list 'regions' [ 1000, 1a3f] { a40} Kern fiasco [ 2000, 9afff] { 99000} Kern fiasco [ 9b000, 9b137] { 138} Root mbi_rt [ e0000, e9ec3] { 9ec4} Sigma0 sigma0 [ f0000, f6177] { 6178} Sigma0 sigma0 [ 140000, 169e37] { 29e38} Root moe [ 170000, 18242b] { 1242c} Root moe [ 1000000, 100e573] { e574} Boot bootstrap [ 1100000, 1876fff] { 777000} Root Module found kernel options (via ELF) at 3000 Sigma0 config ip:000e0100 sp:00000000 Roottask config ip:00140250 sp:00000000 Starting kernel fiasco at 0000120c Hello from Startup::stage2 ARM generic timer: freq=62500000 interval=62500 cnt=5558234 SERIAL ESC: allocated IRQ 57 for serial uart Not using serial hack in slow timer handler. Welcome to L4/Fiasco.OC! L4/Fiasco.OC microkernel on arm Rev: unknown compiled with gcc 4.8.3 20140303 (prerelease) for Broadcom 2836 [] Build: #2 Mon Dec 11 14:06:49 IST 2017 Calibrating timer loop... done. MDB: use page size: 20 MDB: use page size: 12 SIGMA0: Hello! KIP @ 2000 allocated 4KB for maintenance structures SIGMA0: Dump of all resource maps RAM:------------------------ [0:0;fff] [4:9b000;9bfff] [0:9c000;dffff] [0:ea000;effff] [0:f7000;13ffff] [4:140000;169fff] [0:16a000;16ffff] [4:170000;182fff] [0:183000;10fffff] [4:1100000;1876fff] [0:1877000;1effffff] IOMEM:---------------------- [0:20000000;ffffffff] MOE: Hello world MOE: found 499336 KByte free memory MOE: found RAM from 9b000 to 1f000000 MOE: allocated 495 KByte for the page array @0x183000 MOE: virtual user address space [0-bfffffff] MOE: rom name space cap -> [C:103000] MOE: rwfs name space cap -> [C:105000] BOOTFS: [1100000-110012e] [C:107000] l4lx.cfg BOOTFS: [1101000-111a4a4] [C:109000] l4re BOOTFS: [111b000-117c718] [C:10b000] ned BOOTFS: [117d000-1576480] [C:10d000] vmlinuz BOOTFS: [1577000-1877000] [C:10f000] ramdisk-arm.rd MOE: cmdline: moe rom/l4lx.cfg MOE: Starting: rom/ned rom/l4lx.cfg MOE: loading 'rom/ned' Ned says: Hi World! L4Re: unhandled exception: pc=0x1029198 (pfa=205a48) L4Re: Global::l4re_aux->ldr_flags=0

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Trying l4re-snapshot-17.10 on a Wanboard(iMX6Q) hangs at Starting kernel ...
by Sathish Kumar Balasubramaniam -ERS, HCL Tech 18 Dec '17

18 Dec '17

Build machine is Debian 8.10 (jessie) 64-Bit GCC toolchain is gcc-linaro-4.9.4-2017.01-x86_64_arm-linux-gnueabihf I tried to build the l4re-snapshot-17.10 for Freescale iMX6 and the build completed. When i loaded the bootstrap.uimage (both hello and L4Linux-basic) boots till the following U-Boot 2016.11+fslc+gc44711d (Nov 15 2017 - 16:14:11 +0530) CPU: Freescale i.MX6Q rev1.2 at 792 MHz Reset cause: POR Board: Wandboard rev C1 I2C: ready DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 *** Warning - bad CRC, using default environment auto-detected panel HDMI Display: HDMI (1024x768) In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 => ext4load mmc 0 ${loadaddr} /boot/bootstrap.uimage 8790080 bytes read in 628 ms (13.3 MiB/s) => bootm ${loadaddr} ## Booting kernel from Legacy Image at 12000000 ... Image Name: L4 Image #2 Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 8790016 Bytes = 8.4 MiB Load Address: 11000000 Entry Point: 11000000 Verifying Checksum ... OK Loading Kernel Image ... OK Starting kernel ... I have a JTAG BDI-3000 with Cortex-A9 license. Any ideas how to debug the issue ??? ::DISCLAIMER:: ---------------------------------------------------------------------------------------------------------------------------------------------------- The contents of this e-mail and any attachment(s) are confidential and intended for the named recipient(s) only. E-mail transmission is not guaranteed to be secure or error-free as information could be intercepted, corrupted, lost, destroyed, arrive late or incomplete, or may contain viruses in transmission. The e mail and its contents (with or without referred errors) shall therefore not attach any liability on the originator or HCL or its affiliates. Views or opinions, if any, presented in this email are solely those of the author and may not necessarily reflect the views or opinions of HCL or its affiliates. Any form of reproduction, dissemination, copying, disclosure, modification, distribution and / or publication of this message without the prior written consent of authorized representative of HCL is strictly prohibited. If you have received this email in error please delete it and notify the sender immediately. Before opening any email and/or attachments, please check them for viruses and other defects. ---------------------------------------------------------------------------------------------------------------------------------------------------- ::DISCLAIMER:: ---------------------------------------------------------------------------------------------------------------------------------------------------- The contents of this e-mail and any attachment(s) are confidential and intended for the named recipient(s) only. E-mail transmission is not guaranteed to be secure or error-free as information could be intercepted, corrupted, lost, destroyed, arrive late or incomplete, or may contain viruses in transmission. The e mail and its contents (with or without referred errors) shall therefore not attach any liability on the originator or HCL or its affiliates. Views or opinions, if any, presented in this email are solely those of the author and may not necessarily reflect the views or opinions of HCL or its affiliates. Any form of reproduction, dissemination, copying, disclosure, modification, distribution and / or publication of this message without the prior written consent of authorized representative of HCL is strictly prohibited. If you have received this email in error please delete it and notify the sender immediately. Before opening any email and/or attachments, please check them for viruses and other defects. ----------------------------------------------------------------------------------------------------------------------------------------------------

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Re: Add network device to L4Linux
by Yiyang Su 28 Nov '17

28 Nov '17

Hi, Thanks so much for your explanation. Now the L4Linux has access to the network and SD card. The problem was that in order to access these two device in Cubietruck, additional hardware devices must also be provided for L4Linux such as clock source, pin control (pinctrl), power management unit and direct memory access (dma) . To add the required drivers for all hardware devices i have modified some Kconfig and Makefile of L4Linux. Furthermore at the moment Two L4Linux are running and can communicate each other via shmn. I would like to configure as that one L4Linux (call it L1 here) is only allowed to access network device and another one (L2) is only allowed to access SD card device. Now i am struggling how can i provide the right ".io" file for the vbus. First, L1 and L2 require their own devices such as """ Io.add_vbus("l4linux_1", Io.Vi.System_bus { gmacclk = wrap(Hw.GMACTX); miiclk = wrap(Hw.MII); gmacint = wrap(Hw.GMACINT); ethernet = wrap(Hw.NIC); }) Io.add_vbus("l4linux_2", Io.Vi.System_bus { mmc0clk = wrap(Hw.MMC0CLK); regachi5v = wrap(Hw.ACHI5V); regv3v3 = wrap(Hw.V3V3); mmc0 = wrap(Hw.MMC0); }) """ But L1 and L2 still require other common devices such as pinctrl, dma, clk, etc. Here comes the problem, i cannot write the ".io" file like this """ Io.add_vbus("l4linux_1", Io.Vi.System_bus { osc24mclk = wrap(Hw.OSC24M); ahbclk = wrap(Hw.AHB); apb0clk = wrap(Hw.APB0); pinctrl = wrap(Hw.PIO); dmac = wrap(Hw.DMA); gmacclk = wrap(Hw.GMACTX); miiclk = wrap(Hw.MII); gmacint = wrap(Hw.GMACINT); ethernet = wrap(Hw.NIC); }) Io.add_vbus("l4linux_2", Io.Vi.System_bus { osc24mclk = wrap(Hw.OSC24M); ahbclk = wrap(Hw.AHB); apb0clk = wrap(Hw.APB0); pinctrl = wrap(Hw.PIO); dmac = wrap(Hw.DMA); mmc0clk = wrap(Hw.MMC0CLK); regachi5v = wrap(Hw.ACHI5V); regv3v3 = wrap(Hw.V3V3); mmc0 = wrap(Hw.MMC0); }) """ and to boot two L4Linux as: """ loader:start( { caps = { icu = L4.Env.icu, sigma0 = L4.cast(L4.Proto.Factory, L4.Env.sigma0):create(L4.Proto.Sigma0), input = vbus_input:svr(), general = vbus_general:svr(), l4linux_1 = vbus_l4linux_1:svr(), l4linux_2 = vbus_l4linux_2:svr(), }, log = {"IO", "y"}, l4re_dbg = L4.Dbg.Warn, }, "rom/io -vvv rom/l4lx-net-cubi-two.devs rom/l4lx-net-cubi-two.io" ); -- start L4Linux 1 loader:start( { caps = { vbus = vbus_l4linux_1, shmns = shmns:mode("rw"), }, .... } ); -- start L4Linux 2 loader:start( { caps = { vbus = vbus_l4linux_2, shmns = shmns:mode("rw"), }, .... } ); """ There will be conflicting virtual clients because of the two times assignments of the same device to the vbus and the two L4Linux won't be booted. I am stuck here and thinking about to implement a driver server, but don't know if it is the right direction. Any suggestions would be greatly appreciated. Yang

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