l4-hackers

l4-hackers@os.inf.tu-dresden.de

2827 discussions

Workaround to build l4linux for ARM Target
by Leslie Zhai 10 Jan '18

10 Jan '18

Hi l4 hackers, ../arch/l4/arm-mach-l4/l4.c:33:10: fatal error: l4/io/io.h: No such file or directory #include <l4/io/io.h> ^~~~~~~~~~~~ compilation terminated. so I just workaround to `ln -s` manually: build-freescale-imx6/include/l4/io/ ├── io.h -> /data/project/xiangzhai/l4re/l4/pkg/io/libio-io/include/io.h ├── pciids.h -> /data/project/xiangzhai/l4re/l4/pkg/io/io/server/libpciids/include/pciids.h └── types.h -> /data/project/xiangzhai/l4re/l4/pkg/io/libio-io/include/types.h l4re version: svn76 l4linux version: svn57 GNU toolchain: gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11) I think it might be `Makefile` simple issue :) -- Regards, Leslie Zhai - https://reviews.llvm.org/p/xiangzhai/

2 3

Question about vm memory initialization
by nico 10 Jan '18

10 Jan '18

Hi Adam, I started uvmm and found that all ram space allocated to vm are cleared. But I do not need to do that, because uboot has loaded image file to ram, and vm linux would use that image file. Could you tell me where the uvmm did the cleanup? Regards, Nico

4 3

L4Re and Meltdown / Spectre attacks
by Matthias Lange 08 Jan '18

08 Jan '18

Hi, after the dust around the Meltdown and Spectre attacks has settled a bit, you may wonder how Fiasco.OC / L4Re fares with regard to these attacks. Fiasco.OC / L4Re is vulnerable to Meltdown-like attacks because the kernel is mapped into each task. However, the kernel does not map all physical memory but only memory it requires for its own data structures + kernel-user memory required for e.g. UTCBs and vCPU state save areas. Depending on the amount of physical memory and the available page sizes, Fiasco.OC may map it little bit more than that to save TLB entries. That means there can be a slight overlap of user memory that is visible to the kernel. But it is not possible for a thread to read _all_ memory. Because we think that no thread should read information from other threads (pagetables, capability arrays, UTCBs etc.), we plan to change Fiasco.OC to execute in its own address space on Intel CPUs. Against Spectre we do not plan to implement anything right now. We think the attack surface of the kernel is very little (if any) and may be even further reduced with Intel's microcode updates and future compiler/tool mitigations. However, we will observe future discussions and developments and may reassess this in the future. Thank you and regards, Matthias. -- Kernkonzept GmbH. Sitz: Dresden. Amtsgericht Dresden, HRB 31129. Geschäftsführer: Dr.-Ing. Michael Hohmuth

1 0

Fiasco.OC port on Jailhouse
by Muneeswaran Rajendran 19 Dec '17

19 Dec '17

Hi, I trying to understand the porting of fiasco.OC kernel into jailhouse but not able locate the source code of jailhouse porting code for fiasco.OC kernel. Please share the same. I refer this below document to get 'jailhouse/configs/fiasco-demo.c' this file. But i do not find it. https://rtime.felk.cvut.cz/~sojka/students/F3-BP-2016-Baryshnikov-Maxim-bar… Please help me out to find out. Regards, Munees

1 0

exception while running L4linux on raspberry pi 2
by vmc doe 18 Dec '17

18 Dec '17

Hi Adam/l4-hackers, I tried to build l4+l4Re+l4linux for raspberry pi 2. The build was successful, but when I tried to run this in qemu I am getting the following error. Could you pls help me to fix this error? I am new to L4 and L4Re and would like to try out some virtualization options with L4 Microkernel. Could you pls suggest some initial modules or portions where I can start with. Regards vmc L4 Bootstrapper Build: #3 Mon Dec 11 15:24:01 IST 2017, 4.8.3 20140303 (prerelease) Scanning up to 512 MB RAM, starting at offset 32MB Memory size is 512MB (00000000 - 1fffffff) RAM: 0000000000000000 - 000000001fffffff: 524288kB Total RAM: 512MB Scanning fiasco Scanning sigma0 Scanning moe Moving up to 8 modules behind 1100000 moving module 02 { 1823000-18544df } -> { 1914000-19454df } [201952] moving module 01 { 1811000-1822373 } -> { 1902000-1913373 } [70516] moving module 00 { 1786000-1810e23 } -> { 1877000-1901e23 } [568868] moving module 07 { 1486000-1785fff } -> { 1577000-1876fff } [3145728] moving module 06 { 108c000-148547f } -> { 117d000-157647f } [4166784] moving module 05 { 102a000-108b717 } -> { 111b000-117c717 } [399128] moving module 04 { 1010000-10294a3 } -> { 1101000-111a4a3 } [103588] moving module 03 { 100f000-100f12d } -> { 1100000-110012d } [302] Loading fiasco Loading sigma0 Loading moe find kernel info page... found kernel info page (via ELF) at 2000 Regions of list 'regions' [ 1000, 1a3f] { a40} Kern fiasco [ 2000, 9afff] { 99000} Kern fiasco [ 9b000, 9b137] { 138} Root mbi_rt [ e0000, e9ec3] { 9ec4} Sigma0 sigma0 [ f0000, f6177] { 6178} Sigma0 sigma0 [ 140000, 169e37] { 29e38} Root moe [ 170000, 18242b] { 1242c} Root moe [ 1000000, 100e573] { e574} Boot bootstrap [ 1100000, 1876fff] { 777000} Root Module found kernel options (via ELF) at 3000 Sigma0 config ip:000e0100 sp:00000000 Roottask config ip:00140250 sp:00000000 Starting kernel fiasco at 0000120c Hello from Startup::stage2 ARM generic timer: freq=62500000 interval=62500 cnt=5558234 SERIAL ESC: allocated IRQ 57 for serial uart Not using serial hack in slow timer handler. Welcome to L4/Fiasco.OC! L4/Fiasco.OC microkernel on arm Rev: unknown compiled with gcc 4.8.3 20140303 (prerelease) for Broadcom 2836 [] Build: #2 Mon Dec 11 14:06:49 IST 2017 Calibrating timer loop... done. MDB: use page size: 20 MDB: use page size: 12 SIGMA0: Hello! KIP @ 2000 allocated 4KB for maintenance structures SIGMA0: Dump of all resource maps RAM:------------------------ [0:0;fff] [4:9b000;9bfff] [0:9c000;dffff] [0:ea000;effff] [0:f7000;13ffff] [4:140000;169fff] [0:16a000;16ffff] [4:170000;182fff] [0:183000;10fffff] [4:1100000;1876fff] [0:1877000;1effffff] IOMEM:---------------------- [0:20000000;ffffffff] MOE: Hello world MOE: found 499336 KByte free memory MOE: found RAM from 9b000 to 1f000000 MOE: allocated 495 KByte for the page array @0x183000 MOE: virtual user address space [0-bfffffff] MOE: rom name space cap -> [C:103000] MOE: rwfs name space cap -> [C:105000] BOOTFS: [1100000-110012e] [C:107000] l4lx.cfg BOOTFS: [1101000-111a4a4] [C:109000] l4re BOOTFS: [111b000-117c718] [C:10b000] ned BOOTFS: [117d000-1576480] [C:10d000] vmlinuz BOOTFS: [1577000-1877000] [C:10f000] ramdisk-arm.rd MOE: cmdline: moe rom/l4lx.cfg MOE: Starting: rom/ned rom/l4lx.cfg MOE: loading 'rom/ned' Ned says: Hi World! L4Re: unhandled exception: pc=0x1029198 (pfa=205a48) L4Re: Global::l4re_aux->ldr_flags=0

2 1

Trying l4re-snapshot-17.10 on a Wanboard(iMX6Q) hangs at Starting kernel ...
by Sathish Kumar Balasubramaniam -ERS, HCL Tech 18 Dec '17

18 Dec '17

Build machine is Debian 8.10 (jessie) 64-Bit GCC toolchain is gcc-linaro-4.9.4-2017.01-x86_64_arm-linux-gnueabihf I tried to build the l4re-snapshot-17.10 for Freescale iMX6 and the build completed. When i loaded the bootstrap.uimage (both hello and L4Linux-basic) boots till the following U-Boot 2016.11+fslc+gc44711d (Nov 15 2017 - 16:14:11 +0530) CPU: Freescale i.MX6Q rev1.2 at 792 MHz Reset cause: POR Board: Wandboard rev C1 I2C: ready DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 *** Warning - bad CRC, using default environment auto-detected panel HDMI Display: HDMI (1024x768) In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 => ext4load mmc 0 ${loadaddr} /boot/bootstrap.uimage 8790080 bytes read in 628 ms (13.3 MiB/s) => bootm ${loadaddr} ## Booting kernel from Legacy Image at 12000000 ... Image Name: L4 Image #2 Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 8790016 Bytes = 8.4 MiB Load Address: 11000000 Entry Point: 11000000 Verifying Checksum ... OK Loading Kernel Image ... OK Starting kernel ... I have a JTAG BDI-3000 with Cortex-A9 license. Any ideas how to debug the issue ??? ::DISCLAIMER:: ---------------------------------------------------------------------------------------------------------------------------------------------------- The contents of this e-mail and any attachment(s) are confidential and intended for the named recipient(s) only. E-mail transmission is not guaranteed to be secure or error-free as information could be intercepted, corrupted, lost, destroyed, arrive late or incomplete, or may contain viruses in transmission. The e mail and its contents (with or without referred errors) shall therefore not attach any liability on the originator or HCL or its affiliates. Views or opinions, if any, presented in this email are solely those of the author and may not necessarily reflect the views or opinions of HCL or its affiliates. Any form of reproduction, dissemination, copying, disclosure, modification, distribution and / or publication of this message without the prior written consent of authorized representative of HCL is strictly prohibited. If you have received this email in error please delete it and notify the sender immediately. Before opening any email and/or attachments, please check them for viruses and other defects. ---------------------------------------------------------------------------------------------------------------------------------------------------- ::DISCLAIMER:: ---------------------------------------------------------------------------------------------------------------------------------------------------- The contents of this e-mail and any attachment(s) are confidential and intended for the named recipient(s) only. E-mail transmission is not guaranteed to be secure or error-free as information could be intercepted, corrupted, lost, destroyed, arrive late or incomplete, or may contain viruses in transmission. The e mail and its contents (with or without referred errors) shall therefore not attach any liability on the originator or HCL or its affiliates. Views or opinions, if any, presented in this email are solely those of the author and may not necessarily reflect the views or opinions of HCL or its affiliates. Any form of reproduction, dissemination, copying, disclosure, modification, distribution and / or publication of this message without the prior written consent of authorized representative of HCL is strictly prohibited. If you have received this email in error please delete it and notify the sender immediately. Before opening any email and/or attachments, please check them for viruses and other defects. ----------------------------------------------------------------------------------------------------------------------------------------------------

2 1

Re: Add network device to L4Linux
by Yiyang Su 28 Nov '17

28 Nov '17

Hi, Thanks so much for your explanation. Now the L4Linux has access to the network and SD card. The problem was that in order to access these two device in Cubietruck, additional hardware devices must also be provided for L4Linux such as clock source, pin control (pinctrl), power management unit and direct memory access (dma) . To add the required drivers for all hardware devices i have modified some Kconfig and Makefile of L4Linux. Furthermore at the moment Two L4Linux are running and can communicate each other via shmn. I would like to configure as that one L4Linux (call it L1 here) is only allowed to access network device and another one (L2) is only allowed to access SD card device. Now i am struggling how can i provide the right ".io" file for the vbus. First, L1 and L2 require their own devices such as """ Io.add_vbus("l4linux_1", Io.Vi.System_bus { gmacclk = wrap(Hw.GMACTX); miiclk = wrap(Hw.MII); gmacint = wrap(Hw.GMACINT); ethernet = wrap(Hw.NIC); }) Io.add_vbus("l4linux_2", Io.Vi.System_bus { mmc0clk = wrap(Hw.MMC0CLK); regachi5v = wrap(Hw.ACHI5V); regv3v3 = wrap(Hw.V3V3); mmc0 = wrap(Hw.MMC0); }) """ But L1 and L2 still require other common devices such as pinctrl, dma, clk, etc. Here comes the problem, i cannot write the ".io" file like this """ Io.add_vbus("l4linux_1", Io.Vi.System_bus { osc24mclk = wrap(Hw.OSC24M); ahbclk = wrap(Hw.AHB); apb0clk = wrap(Hw.APB0); pinctrl = wrap(Hw.PIO); dmac = wrap(Hw.DMA); gmacclk = wrap(Hw.GMACTX); miiclk = wrap(Hw.MII); gmacint = wrap(Hw.GMACINT); ethernet = wrap(Hw.NIC); }) Io.add_vbus("l4linux_2", Io.Vi.System_bus { osc24mclk = wrap(Hw.OSC24M); ahbclk = wrap(Hw.AHB); apb0clk = wrap(Hw.APB0); pinctrl = wrap(Hw.PIO); dmac = wrap(Hw.DMA); mmc0clk = wrap(Hw.MMC0CLK); regachi5v = wrap(Hw.ACHI5V); regv3v3 = wrap(Hw.V3V3); mmc0 = wrap(Hw.MMC0); }) """ and to boot two L4Linux as: """ loader:start( { caps = { icu = L4.Env.icu, sigma0 = L4.cast(L4.Proto.Factory, L4.Env.sigma0):create(L4.Proto.Sigma0), input = vbus_input:svr(), general = vbus_general:svr(), l4linux_1 = vbus_l4linux_1:svr(), l4linux_2 = vbus_l4linux_2:svr(), }, log = {"IO", "y"}, l4re_dbg = L4.Dbg.Warn, }, "rom/io -vvv rom/l4lx-net-cubi-two.devs rom/l4lx-net-cubi-two.io" ); -- start L4Linux 1 loader:start( { caps = { vbus = vbus_l4linux_1, shmns = shmns:mode("rw"), }, .... } ); -- start L4Linux 2 loader:start( { caps = { vbus = vbus_l4linux_2, shmns = shmns:mode("rw"), }, .... } ); """ There will be conflicting virtual clients because of the two times assignments of the same device to the vbus and the two L4Linux won't be booted. I am stuck here and thinking about to implement a driver server, but don't know if it is the right direction. Any suggestions would be greatly appreciated. Yang

2 1

Porting Fiasco + L4Re to Raspberry Pi 2
by Antoine DEBUT 26 Nov '17

26 Nov '17

Hello l4-hackers, I am currently working on porting the Fiasco.OC micro kernel onto the Raspberry pi 2. Therefore, I am struggling with memory mapping, and I encounter the following error when launching the default 'hello' entry: L4 Bootstrapper Build: #2 Tue Feb 23 11:57:19 CET 2016, 4.8.3 20140303 (prerelease) Scanning up to 1024 MB RAM, starting at offset 32MB Memory size is 1024MB (00000000 - 3fffffff) RAM: 0000000000000000 - 000000003fffffff: 1048576kB Total RAM: 1024MB Scanning fiasco Scanning sigma0 Scanning moe Moving up to 5 modules behind 1100000 moving module 02 { 10db000-110c4d7 } -> { 11cc000-11fd4d7 } [201944] moving module 01 { 10c9000-10da373 } -> { 11ba000-11cb373 } [70516] moving module 00 { 1043000-10c889f } -> { 1134000-11b989f } [546976] moving module 04 { 1029000-10425af } -> { 111a000-11335af } [103856] moving module 03 { 100f000-102849b } -> { 1100000-111949b } [103580] Loading fiasco Loading sigma0 Loading moe find kernel info page... found kernel info page at 0x2000 Regions of list 'regions' [ 1000, 1aff] { b00} Kern fiasco [ 2000, 92fff] { 91000} Kern fiasco [ 93000, 930eb] { ec} Root mbi_rt [ c0000, c9c33] { 9c34} Sigma0 sigma0 [ d0000, d6177] { 6178} Sigma0 sigma0 [ 140000, 16905b] { 2905c} Root moe [ 170000, 17b58b] { b58c} Root moe [ 1000000, 100e4ff] { e500} Boot bootstrap [ 1100000, 1133fff] { 34000} Root Module API Version: (87) experimental Sigma0 config ip:000c0100 sp:00000000 Roottask config ip:00140250 sp:00000000 Starting kernel fiasco at 000012b8 Non-HYP kernel detected but running in HYP mode, switching back. Hello from Startup::stage2 Assertion failed at /home/adebut/Documents/snapshotTest/l4re-snapshot-2015123115/src/kernel/fiasco/src/kern/buddy_alloc.cpp:101: (unsigned long)block >= _base Press any key to reboot. I am currently working on the latest snapshot (2015123115), with U-Boot as a bootloader, and testing on a real board (Raspberry Pi 2 model B V1.1). The entry built is the standard 'hello', and I use the ramdisk-arm.rd given in the snapshot. I did add a custom Bsp for the board, mainly based on the first Raspberry Pi except for the Base Address, that is 0x3F000000 instead of the first Pi's 0x20000000. I highly think that it is an address configuration problem, because it first happened when I did expand the RAM size to 1024MB. With further investigation, I found out that it was the kernel memory allocation that causes this error, and suspect an incorrect MMU mapping. This suspicion comes from the fact that the assertion takes the address _base (0xf0400000) and the currently allocated block (0xee100000). I did not modify any parameter in the kern/arm/mem_layout-arm.cpp file on the Fiasco directory, which provides the default ARM addressing. Maybe that's where my error comes from ? How can I correctly configure my memory mapping, besides what I already configure in the Bsp (given in attachment) ? Also, it is the first time that I am assigned for porting a system, do you have some hints, like important steps to follow ? I am pretty sure it is a newbie error, but I cannot figure it out for now :( Thanks in advance for your time, -- Antoine Debut EPITA 2016 - GISTRE

3 7

Does the latest version of L4Re support 64bit VMM?
by nico 20 Nov '17

20 Nov '17

Hi, The latest kernel supports armv8 and 64bit Hyp mode. Does that mean we can run a guest OS in VM, such as 64bit Linux? Does L4Re provide the corresponding interfaces for that? Regards, Nico

2 1

Booting L4Re with qemu-system-arm: Panic in sigma0
by Leslie Zhai 01 Nov '17

01 Nov '17

Hi L4 hackers, $ svn info Path: . Working Copy Root Path: /data/project/l4re URL: https://svn.l4re.org/repos/oc/l4re/trunk Relative URL: ^/trunk Repository Root: https://svn.l4re.org/repos/oc/l4re Repository UUID: d050ee49-bd90-4346-b210-929a50b99cfc Revision: 75 Node Kind: directory Schedule: normal Last Changed Author: l4check Last Changed Rev: 75 Last Changed Date: 2017-10-15 19:49:39 +0800 (Sun, 15 Oct 2017) My Fiasco build config: # # Automatically generated file; DO NOT EDIT. # Fiasco configuration # CONFIG_HAS_FPU_OPTION=y CONFIG_HAS_SERIAL_OPTION=y CONFIG_HAS_JDB_GZIP_OPTION=y # # Target configuration # # CONFIG_IA32 is not set # CONFIG_AMD64 is not set CONFIG_ARM=y # CONFIG_MIPS is not set CONFIG_PF_INTEGRATOR=y # CONFIG_PF_REALVIEW is not set # CONFIG_PF_SUNXI is not set # CONFIG_PF_BCM283X is not set # CONFIG_PF_SA1100 is not set # CONFIG_PF_XSCALE is not set # CONFIG_PF_ARMADA38X is not set # CONFIG_PF_KIRKWOOD is not set # CONFIG_PF_TEGRA is not set # CONFIG_PF_LAYERSCAPE is not set # CONFIG_PF_IMX is not set # CONFIG_PF_RCAR3 is not set # CONFIG_PF_EXYNOS is not set # CONFIG_PF_S3C2410 is not set # CONFIG_PF_OMAP is not set # CONFIG_PF_ZYNQ is not set CONFIG_BSP_NAME="integrator" CONFIG_CAN_ARM_CPU_926=y CONFIG_CAN_ARM_CPU_1176=y CONFIG_ABI_VF=y CONFIG_ARM_926=y # CONFIG_ARM_1176 is not set CONFIG_FPU=y CONFIG_ARM_ALIGNMENT_CHECK=y CONFIG_ARM_EM_STD=y CONFIG_ARM_CPU_ERRATA=y # # Kernel options # # CONFIG_CONTEXT_8K is not set CONFIG_CONTEXT_4K=y CONFIG_FINE_GRAINED_CPUTIME=y CONFIG_SCHED_FIXED_PRIO=y # CONFIG_SCHED_WFQ is not set # CONFIG_SCHED_FP_WFQ is not set # # Debugging # CONFIG_INLINE=y # CONFIG_NDEBUG is not set # CONFIG_NO_FRAME_PTR is not set CONFIG_STACK_DEPTH=y CONFIG_LIST_ALLOC_SANITY=y CONFIG_SERIAL=y CONFIG_JDB=y CONFIG_JDB_LOGGING=y CONFIG_JDB_GZIP=y # CONFIG_JDB_ACCOUNTING is not set # CONFIG_WARN_NONE is not set # CONFIG_WARN_WARNING is not set CONFIG_WARN_ANY=y # # ARM debugging options # CONFIG_VMEM_ALLOC_TEST=y CONFIG_DEBUG_KERNEL_PAGE_FAULTS=y # # Compiling # CONFIG_CC="gcc" CONFIG_CXX="g++" CONFIG_HOST_CC="gcc" CONFIG_HOST_CXX="g++" CONFIG_MAINTAINER_MODE=y CONFIG_LABEL="" CONFIG_EXPERIMENTAL=y CONFIG_PERF_CNT=y CONFIG_BIT32=y CONFIG_WARN_LEVEL=2 CONFIG_XARCH="arm" CONFIG_ABI="vf" My L4Re build config: # Automatically generated. Don't edit BID_COMPILER_TYPE=gcc BUILD_SYSTEMS=arm_armv5te arm_armv5te-l4f CONFIG_ARCH_ENABLE_STACK_PROTECTOR=y CONFIG_BID_GCC_ENABLE_STACK_PROTECTOR=y CONFIG_BID_GCC_STACK_PROTECTOR=y CONFIG_BUILD_ABI="l4f" CONFIG_BUILD_ABI_l4f=y CONFIG_BUILD_ARCH="arm" CONFIG_BUILD_ARCH_arm=y CONFIG_CPU_ARM_ARMV5TE=y CONFIG_CPU="armv5te" CONFIG_CTAGS="ctags" CONFIG_DROPS_INSTDIR="/path/to/l4re" CONFIG_DROPS_STDDIR="/path/to/l4re" CONFIG_ETAGS="etags" CONFIG_LEX="flex" CONFIG_MAKECONFS_ADD="" CONFIG_YACC="yacc" GCCDIR=/usr/lib/gcc/arm-linux-gnueabi/6.1.1 GCCFORTRANAVAIL= GCC_HAS_ATOMICS= GCCINCFIXEDPATH=/usr/lib/gcc/arm-linux-gnueabi/6.1.1/include-fixed GCCLIB_EH=/usr/lib/gcc/arm-linux-gnueabi/6.1.1/libgcc_eh.a GCCLIB_FILE_crtbegin.o=/usr/lib/gcc/arm-linux-gnueabi/6.1.1/crtbegin.o GCCLIB_FILE_crtbeginS.o=/usr/lib/gcc/arm-linux-gnueabi/6.1.1/crtbeginS.o GCCLIB_FILE_crtbeginT.o=/usr/lib/gcc/arm-linux-gnueabi/6.1.1/crtbeginT.o GCCLIB_FILE_crtend.o=/usr/lib/gcc/arm-linux-gnueabi/6.1.1/crtend.o GCCLIB_FILE_crtendS.o=/usr/lib/gcc/arm-linux-gnueabi/6.1.1/crtendS.o GCCLIB_HOST=/usr/lib/gcc/arm-linux-gnueabi/6.1.1/libgcc.a GCCLIB_S_SO= GCCMAJORVERSION=6 GCCMINORVERSION=1 GCCNOSTACKPROTOPT=-fno-stack-protector GCCPATCHLEVEL=1 GCCSTACKPROTALLOPT=-fstack-protector-all GCCSTACKPROTOPT=-fstack-protector GCCSYSLIBDIRS=-L/usr/lib/gcc/arm-linux-gnueabi/6.1.1/ -L/usr/lib/gcc/arm-linux-gnueabi/6.1.1/../../../../arm-linux-gnueabi/lib/arm-linux-gnueabi/6.1.1/ -L/usr/lib/gcc/arm-linux-gnueabi/6.1.1/../../../../arm-linux-gnueabi/lib/ -L/usr/arm-linux-gnu/sys-root/lib/arm-linux-gnueabi/6.1.1/ -L/usr/arm-linux-gnu/sys-root/lib/ -L/usr/arm-linux-gnu/sys-root/usr/lib/arm-linux-gnueabi/6.1.1/ -L/usr/arm-linux-gnu/sys-root/usr/lib/ GCCVERSION=6 HOST_SYSTEM=linux INT_CPP_NAME=cc1 INT_CXX_NAME=cc1plus INT_LD_NAME=arm-linux-gnu-ld LD_EMULATION=armelf_linux_eabi LD_GENDEP_PREFIX=LD_PRELOAD=libgendep.so LD_LIBRARY_PATH=/data/project/xiangzhai/l4re/l4/build-arm/tool/gendep/64:/data/project/xiangzhai/l4re/l4/build-arm/tool/gendep/32 LD_HAS_HASH_STYLE_OPTION=n LDVERSION=227-3 include /data/project/xiangzhai/l4re/l4/build-arm/.config.indep include /data/project/xiangzhai/l4re/l4/build-arm/.config.platform Booting L4Re with qemu-system-arm: $ make qemu CROSS_COMPILE=arm-linux-gnu- E=hello MODULE_SEARCH_PATH=/data/project/xiangzhai/l4re/kernel/fiasco/build-arm make[1]: Entering directory '/data/project/xiangzhai/l4re/l4' Image size(s) in bytes: bootstrap_hello.elf: 1279488 Start address: 0x1000000 --> Build-Nr: 6 QEMU-cmd: qemu-system-arm -kernel /data/project/xiangzhai/l4re/l4/build-arm/images/bootstrap.elf -serial stdio -M integratorcp -m 256 L4 Bootstrapper Build: #6 Tue Oct 31 15:50:55 CST 2017, 6.1.1 20160621 (Red Hat Cross 6.1.1-2) Scanning up to 256 MB RAM, starting at offset 32MB Memory size is 256MB (00000000 - 0fffffff) RAM: 0000000000000000 - 000000000fffffff: 262144kB Total RAM: 256MB Scanning fiasco Scanning sigma0 Scanning moe Moving up to 5 modules behind 1100000 moving module 02 { 10e7000-11284af } -> { 11d8000-12194af } [267440] moving module 01 { 10d5000-10e6343 } -> { 11c6000-11d7343 } [70468] moving module 00 { 1053000-10d4edb } -> { 1144000-11c5edb } [532188] moving module 04 { 1031000-1052697 } -> { 1122000-1143697 } [136856] moving module 03 { 100f000-1030473 } -> { 1100000-1121473 } [136308] Loading fiasco Loading sigma0 Loading moe find kernel info page... found kernel info page (via ELF) at 2000 Regions of list 'regions' [ 1000, 193f] { 940} Kern fiasco [ 2000, 8efff] { 8d000} Kern fiasco [ 8f000, 8f0eb] { ec} Root mbi_rt [ e0000, eb16b] { b16c} Sigma0 sigma0 [ f0000, f517b] { 517c} Sigma0 sigma0 [ 140000, 1711df] { 311e0} Root moe [ 180000, 18c4eb] { c4ec} Root moe [ 1000000, 100e4f7] { e4f8} Boot bootstrap [ 1100000, 1143fff] { 44000} Root Module found kernel options (via ELF) at 3000 Sigma0 config ip:000e0100 sp:00000000 Roottask config ip:00140254 sp:00000000 Starting kernel fiasco at 00001118 Hello from Startup::stage2 FPU: Initialize FPU0: Subarch: 1, Part: 10, Rev: 0, Var: 9, Impl: 41 KERNEL: Warning: Buddy::alloc: Size mismatch: 1c000 v 20000 SERIAL ESC: allocated IRQ 1 for serial uart Not using serial hack in slow timer handler. Welcome to L4/Fiasco.OC! L4/Fiasco.OC microkernel on arm Rev: 362fdae-dirty compiled with gcc 6.1.1 20160621 (Red Hat Cross 6.1.1-2) for Integrator [] Build: #2 Tue Oct 31 15:39:15 CST 2017 Calibrating timer loop... done. MDB: use page size: 20 MDB: use page size: 12 EXCEPTION: (00) Why undef insn? pfa=00002000, error=00000000 psr=20000110 R[0]: 00002000 00000000 00000000 000e01d0 000f0004 00002000 000f0030 00000000 R[8]: 00000000 00000000 00000000 000f281c 000f2808 00000000 00000000 000e01d4 KERNEL: Warning: Sigma0 raised an exception --> HALT Panic: ... --------------------------------------------------------------------- CPU 0 [f001519c]: abort jdb: Then how to use addr2line to find the root cause? please give me some hint, thanks a lot! $ arm-linux-gnu-addr2line -p -i -e bin/arm_armv5te/bootstrap.elf -a 00002000 Because 0001-Fix-invalid-initialization-in-new.patch has been already merged into svn trunk, so this http://os.inf.tu-dresden.de/pipermail/l4-hackers/2017/008111.html might not fix my issue, but as Sarah mentioned "looks like a compiler issue"? $ arm-linux-gnu-gcc -v Using built-in specs. COLLECT_GCC=arm-linux-gnu-gcc COLLECT_LTO_WRAPPER=/usr/libexec/gcc/arm-linux-gnueabi/6.1.1/lto-wrapper Target: arm-linux-gnueabi Configured with: ../gcc-6.1.1-20160621/configure --bindir=/usr/bin --build=x86_64-redhat-linux-gnu --datadir=/usr/share --disable-decimal-float --disable-dependency-tracking --disable-gold --disable-libgcj --disable-libgomp --disable-libmpx --disable-libquadmath --disable-libssp --disable-libunwind-exceptions --disable-shared --disable-silent-rules --disable-sjlj-exceptions --disable-threads --with-ld=/usr/bin/arm-linux-gnu-ld --enable-__cxa_atexit --enable-checking=release --enable-gnu-unique-object --enable-initfini-array --enable-languages=c,c++ --enable-linker-build-id --enable-lto --enable-nls --enable-obsolete --enable-plugin --enable-targets=all --exec-prefix=/usr --host=x86_64-redhat-linux-gnu --includedir=/usr/include --infodir=/usr/share/info --libexecdir=/usr/libexec --localstatedir=/var --mandir=/usr/share/man --prefix=/usr --program-prefix=arm-linux-gnu- --sbindir=/usr/sbin --sharedstatedir=/var/lib --sysconfdir=/etc --target=arm-linux-gnueabi --with-bugurl=http://bugzilla.redhat.com/bugzilla/ --with-isl --with-newlib --with-plugin-ld=/usr/bin/arm-linux-gnu-ld --with-sysroot=/usr/arm-linux-gnu/sys-root --with-system-libunwind --with-system-zlib --without-headers --with-tune=cortex-a8 --with-arch=armv7-a --with-float=hard --with-fpu=vfpv3-d16 --with-abi=aapcs-linux --enable-gnu-indirect-function --with-linker-hash-style=gnu Thread model: single gcc version 6.1.1 20160621 (Red Hat Cross 6.1.1-2) (GCC) -- Regards, Leslie Zhai - https://reviews.llvm.org/p/xiangzhai/

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