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read string from server array error!
by fang zhengshu 15 Jul '09

15 Jul '09

2009/7/8 fang zhengshu <fangzhsh07(a)gmail.com> > > > 2009/7/6 fang zhengshu <fangzhsh07(a)gmail.com> > >> hi all, >> when I write a function in the IDL file, there is a problem:want to write >> a different-length string to a array and then read parts of the array to >> another string like: >> >> interface test{ >> int write([string]char* str, int len); >> int read([out,prealloc_client, size_is(size), prealloc_server]char >> str[], int size); >> }; >> > I modify the idl file as the following: int write([in,string]char *str, int len) int read([out, prealloc_client]char *str, int len) there no error when compile it,but > >> I have defined a fixed size array in the server like array[256]. >> In the write() function I write a different length string to the array, >> then I want to read parts or all of the array in the read() function, the >> process will be like the following: >> >> string[len] str[size] >> | ^ >> | | >> --------->array[256] -----------| >> >> >> but when I put the function above and compile it, there are some error >> happen. I have change the size_is() with length_is() or max_is(), but there >> still error when I compile it. I know if I define a fix array str[256] the >> code can be work, but I just want to use a unfixed length array to get the >> string. >> could someone please give me some advice?if I describe the problem >> clearly, please let me know. >> >> thank you! >> >> I don't know whether I describe what I want to do clearly,so I put the > simple code below: > > read-client > write-client > #define STR_TO 30 > #define STR_FROM 30 > ... > ... > char str_to[SRR_TO]; > char str_from[STR_FROM]; > ... > ... > read(str_to, STR_TO); > write(str_from, STR_FROM); > ... > ... > > server > #define SIZE 256 > ... > char string[SIZE]; > ... > int write(char > *str_from, int str_from) > { > //write str_from size chars of str_from array to the > string array which is in server > } > int read(char *str_to, > int str_to) > { > //read str_to size chars from the string array which is in > server to str_to > } > > Then I define write functions as the above in a .idl file,but when I > compile it,there will be the following error: > terminate called after throwing an instance of 'std::out_of_range' > what(): CBEMsgBuffer::IsEarlier > make[1]: *** [test-server.c] Aborted > make[1]: *** [test-server.c] Deleting file `test-sys.h' > make[1]: *** [test-server.c] Deleting file `test-client.h' > make[1]: *** [test-server.c] Deleting file `test-client.c' > make: *** [/home/l4/tudos/build/pkg/ > fifo/idl/OBJ-x86-l4v2] Error 2 > > must we use the format as the dice manual below?: > int read([out, prealloc_client, size_is(len)] char **str, [out,in]int *len) > and when I modify the function as > int read([out, prealloc_client, prealloc_server, size_is(len)] char *str, > [out,in]int *len) > there is no error when compile it,but there will be another error called > :fpage > could you give me some advice for the read function? > thank you. > -- > fang, > when I run the test in qemu, the error come out: fifo | L4RM: [PF] read at 0x00002000, ip 01800aa1, src B.02 fifo | [B.0] l4rm/lib/src/pagefault.c:81:__unknown_pf(): fifo | unhandled page fault the execute code of fifo binary is : ... /home/l4/tudos/build/pkg/fifo/idl/OBJ-x86-l4v2/fifo-server.c:259 l4_msgdope_t _dice_size_dope; l4_msgdope_t _dice_send_dope; l4_umword_t _word[2]; } _word; } fifo_fifo_read_msg_buffer_t; l4_umword_t _dice_str_size = (str) ? (_dice_strlen(str)+1) : 0; 1800a8b: 85 db test %ebx,%ebx 1800a8d: 0f 84 f9 00 00 00 je 1800b8c <fifo_dispatch+0x21c> 1800a93: 80 3b 00 cmpb $0x0,(%ebx) 1800a96: 0f 84 11 01 00 00 je 1800bad <fifo_dispatch+0x23d> 1800a9c: 31 c0 xor %eax,%eax 1800a9e: 66 90 xchg %ax,%ax 1800aa0: 40 inc %eax 1800aa1: 80 3c 18 00 cmpb $0x0,(%eax,%ebx,1) 1800aa5: 75 f9 jne 1800aa0 <fifo_dispatch+0x130> 1800aa7: 8d 58 01 lea 0x1(%eax),%ebx ... the fifo-server.c:259 code is: inline void fifo_read_marshal (CORBA_Object _dice_corba_obj, int _dice_return /* out */, l4_msgtag_t *_dice_tag, char* str /* out */, fifo_msg_buffer_t *_dice_msg_buffer, CORBA_Server_Environment *_dice_corba_env) { ... l4_umword_t _dice_str_size = (str) ? (_dice_strlen(str)+1) : 0; ... so anyone can give me some advice? thank you! -- fang,

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Re: l4-hackers Digest, Vol 72, Issue 8
by fang zhengshu 08 Jul '09

08 Jul '09

hi all, when I write a function in the IDL file, there is a problem:want to write a different-length string to a array like: interface test{ int write([string]char* str, int len); int read([out,prealloc_client, size_is(size), prealloc_server]char str[], int size); }; I have defined a fixed size array in the server like array[256]. In the write() function I write a different length string to the array, then I want to read parts or all of the array in the read() function, the process will be like the following: string[len] str[size] | ^ | | --------->array[256] -----------| but when I put the function above and compile it, there are some error happen. I have change the size_is() with length_is() or max_is(), but there still error when I compile it. I know if I define a fix array str[256] the code can be work, but I just want to use a unfixed length array to get the string. could someone please give me some advice?if I describe the problem clearly, please let me know. thank you! -- fang,

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running cpu_reserve examples
by Andre Puschmann 29 Jun '09

29 Jun '09

Hi list, I am playing with the examples in package cpu_reserve (i.e. res_rt_sched). However, for some reason the code doesn't work as expected. In the worker-thread the function l4_rt_next_period() returns error nr 32 which is an IPC error, I guess its waiting for a msg from the reservation server here. Here is the sample output (qemu log): Welcome to Fiasco(ia32)! DD-L4(v2)/ia32 microkernel (C) 1998-2009 TU Dresden Rev: r429 compiled with gcc 4.2.4 for Intel Pentium [] Performance-critical config option(s) detected: CONFIG_NDEBUG is off Enabling special fully nested mode for PIC Using the PIT (i8254) on IRQ 0 for scheduling SERIAL ESC: allocated IRQ 4 for serial uart SERIAL ESC: allocated IRQ 4 for serial uart Not using serial hack in slow timer handler. Absolute KIP Syscalls using: Sysenter CPU: GenuineIntel (6:3:3:0) Model: Pentium II (Klamath) at 2528 MHz 32 KB L1 I Cache (8-way associative, 64 bytes per line) 32 KB L1 D Cache (8-way associative, 64 bytes per line) 2048 KB L2 U Cache (8-way associative, 64 bytes per line) Freeing init code/data: 20480 bytes (5 pages) Calibrating timer loop... done. SIGMA0: Hello! KIP @ 1000 Found Fiasco: KIP syscalls: yes allocated 4KB for maintenance structures Roottask. Command line found: "(nd)/modules/roottask" 260656kB ( 254MB) total RAM (reported by bootloader) 232760kB ( 228MB) received RAM from Sigma0 6604kB ( 7MB) reserved RAM for RMGR Received I/O ports 0000-ffff Attached irqs = [ <!0> 1 <!2> 3 <!4> 5 6 7 8 9 A B C D E F 10 11 ] Roottask: Loading 6 modules. #05: loading "(nd)/modules/l4io" from [0212b000-02398e9a] to [00c20000-00c443b5][00c45000-00cb3000] entry at 0005a06c via trampoline page code symbols at [0ea31000-0ea87000] (344kB), lines at [0ea17000-0ea31000] (104kB) #06: loading "(nd)/modules/dm_phys" from [02399000-02434537] to [01500000-015138d7][01514000-0151e000] entry at 0005b070 via trampoline page code symbols at [0ea12000-0ea17000] (20kB), lines at [0ea04000-0ea12000] (56kB) #07: loading "(nd)/modules/names" from [02435000-0247685b] to [002d0000-002d67b7][002d7000-002e2000] entry at 0005c06c via trampoline page code symbols at [0ea02000-0ea04000] (8kB), lines at [0e9fc000-0ea02000] (24kB) #08: loading "(nd)/modules/log" from [02477000-024b5702] to [00400000-00406eca][00407000-00439828] entry at 0005d06c via trampoline page code symbols at [0e9fa000-0e9fc000] (8kB), lines at [0e9f4000-0e9fa000] (24kB) #09: loading "(nd)/modules/cpu_reserved" from [024b6000-0256af2c] to [009b0000-009cc631][009cd000-009e4000] entry at 0005e074 via trampoline page code symbols at [0e9ef000-0e9f4000] (20kB), lines at [0e9da000-0e9ef000] (84kB) #0a: loading "(nd)/modules/res_rt_sched" from [0256b000-02601c8b] to [01000000-01017a61][01018000-0102f000] entry at 00060074 via trampoline page code symbols at [0e9d5000-0e9da000] (20kB), lines at [0e9c3000-0e9d5000] (72kB) cpu_rese| Scheduling granularity: 1000�s res_rt_s| main(): Using cpu reservation server res_rt_s| [A.3] cpu_reserve/examples/res_rt_sched/main.c:55:worker(): res_rt_s| Error: l4_rt_next_period(): Unknown (unregistered) error res_rt_s| [A.3] cpu_reserve/examples/res_rt_sched/main.c:68:worker(): res_rt_s| Error: l4_rt_next_period(): Unknown (unregistered) error res_rt_s| [A.3] cpu_reserve/examples/res_rt_sched/main.c:68:worker(): ... Any ideas what I am doing wrong? Thanks in advance. Best regards, Andre

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How to check out ddekit
by Zheng Da 23 Jun '09

23 Jun '09

Hi, I'd like to get the source code of ddekit but it seems that I cannot get it from the SVN repository. I first do $ svn co -N http://svn.tudos.org/repos/tudos/trunk tudos Then I followed the step in http://www.inf.tu-dresden.de/index.php?node_id=1584&ln=en, but always get some error whenever checking out the linux header files. da-zhengs-macbook:tudos dazheng$ ./repomgr co l4env ... A l4/pkg/linux-24-headers/include/linux/netfilter_ipv4/ipt_REJECT.h svn: In directory 'l4/pkg/linux-24-headers/include/linux/netfilter_ipv4' svn: Can't copy 'l4/pkg/linux-24-headers/include/linux/netfilter_ipv4/.svn/tmp/text-base/ipt_TCPMSS.h.svn-base' to 'l4/pkg/linux-24-headers/include/linux/netfilter_ipv4/.svn/tmp/ipt_TCPMSS.h.tmp.tmp': No such file or directory svn update failed at ./repomgr line 349. da-zhengs-macbook:pkg dazheng$ svn up linux-26-headers ... A linux-26-headers/include/linux/netfilter_ipv4/ipt_REJECT.h svn: In directory 'linux-26-headers/include/linux/netfilter_ipv4' svn: Can't move source to dest svn: Can't move 'linux-26-headers/include/linux/netfilter_ipv4/.svn/tmp/prop-base/ipt_TCPMSS.h.svn-base' to 'linux-26-headers/include/linux/netfilter_ipv4/.svn/prop-base/ipt_TCPMSS.h.svn-base': No such file or directory da-zhengs-macbook:pkg dazheng$ svn up dde ... A dde/linux26/contrib/include/linux/netfilter_ipv4/ipt_REJECT.h svn: In directory 'dde/linux26/contrib/include/linux/netfilter_ipv4' svn: Can't copy 'dde/linux26/contrib/include/linux/netfilter_ipv4/.svn/tmp/text-base/ipt_TCPMSS.h.svn-base' to 'dde/linux26/contrib/include/linux/netfilter_ipv4/.svn/tmp/ipt_TCPMSS.h.tmp.tmp': No such file or directory Is the SVN repository correct? Zheng Da

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Invalid TCB Access for thread creation in L4Linux
by Sean 14 Jun '09

14 Jun '09

Dear all Now I try to add some functions and data structures in Fiasco. I had added several data structures into "class Context" and implement some functions to manipulate these data structures. My goal is to add multiple ready queues in Fiasco. So I add the corresponding enqueue function in ready_enqueue() to add the Context into my own ready queue. (But I don't change the way to choose highest Context, I only add the queue and try the functionality of these queue.) It seems to be valid for simple environment. But when I load L4Linux and I want to group all threads owned by L4Linux into my ready queue, it got some unpredictable page fault error. ------------------------------------------------------------------------------- ... mice: PS/2 mouse device common for all mice TCP cubic registered NET: Registered protocol family 17 Freeing init memory: 128K init started: BusyBox v1.13.2 (2009-05-13 02:16:43 CST) starting pid 13, tty '/dev/console': '-/etc/init.d/rcS' Fiasco BUG: pfa=c0440084 err=400017 pc=f001f14c --Fiasco BUG: Invalid TCB access (locked)------------------PC: f00080a8 [rcS] (10.00) jdb: ------------------------------------------------------------------------------- The error is caused from the enqueue function which changes the data structures in class Context. But the error sometimes happened before l4x.idler0 thread creation, sometimes I can get into shell correctly and error happened when I use unix commands (which creates new thread for this unix commands). The error is unpredictable. Because the other threads can work correctly, I guest that there are some issues in L4Linux to cause this error from the modification of class Context. Can anyone give me any idea? Thanks very much!! Best Regards, Sean

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Re: [ANNOUNCE] Introducing Codezero
by John van V. 13 Jun '09

13 Jun '09

Thank you. I gave the idea a little thought, and I think that the next OS needs another layer on top of the UI technology that directly talks to the user. I think that to directly integrate the user into the system, there has to be some kind of mind-mapping interaction with the OS as part of the capabilities that are offered to the user in the UI. Beyond this, the user needs to integrate into the "cloud," which is the rest of society, through the mind mapping, which then becomes minds-mapping. (??) John On Thu, Jun 11, 2009 at 12:03 PM, Bahadir Balban<bahadir(a)l4dev.org> wrote: > John van V. wrote: >> >> Hello Bahadir, >> >> Sounds interesting. I have two questions: >> >> You mention a "native OS components in one system." Does it >> anticipate a specific UI? >> >> Also is it specifically for ARM? >> >> Thanks in advance, John > > Hi John, > > Currently it contains two userspace components, the memory management and > vfs services. So there is no UI yet. On the next few releases there will be > a port of the Xynth windowing system. > > It is very portable, only that ARM is supported as the first architecture. > > > Thanks, > > -- > Bahadir Balban > -- Empathy http://thinman.com/empathy Photography http://thinman.com/photography Technology http://thinman.com

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[Fwd: FW: MSR OS Group RSDE Position]
by Ronald Aigner 12 Jun '09

12 Jun '09

More info on Microsoft Research: http://research.microsoft.com More info about Galen Hunt: http://research.microsoft.com/en-us/people/galenh/ Regards, Ron. -------- Original Message -------- From: Galen Hunt Sent: Thursday, June 11, 2009 8:51 Subject: MSR OS Group RSDE Position Friends, The Microsoft Research (MSR) Redmond OS group is looking for an RSDE. We're looking for someone who can code like the wind and is interesting in gaining great breadth of experience. I think no other group in Microsoft offers an equivalent opportunity to write OS, compiler, and tools code. As an example, one of the RSDEs in my group implemented ACPI for Singularity, most of an ARM JIT for the CLR, and a file system in the last two years. We're favorable toward candidates who want to do a tour of duty in MSR before jumping back to product, or want to build their experience and publication record before going to a top-five school for graduate work. If you know of anyone who would be interested, please ask them to contact me. Here is the job description: The Microsoft Research Operating Systems Group is looking for an exceptionally strong engineer (RSDE) to join our team. We are a tight-knit, world-leading research team with the charter of prototyping new OS-related advances and working closely with product teams on tech transfer. Our team frequently publishes in top conferences such as SOSP, OSDI, PLDI, and POPL. Three of 23 papers in SOSP 2009 were co-authored by members of our group. In the recent past, we built the Singularity OS, prototyped a file system for Phase Change Memory (PCM), published the first research on verification of practical garbage collectors, and experimented with new OS configurations for mobile computing. We are looking for a candidate with exceptionally strong coding skills and a passion to change the world. The ideal candidate will have a B.S. or higher in computer science or a closely related field and at least 3 years of experience either building product quality code or coding in a research environment. Experience with C, C++, and assembly is required. Experience writing kernel-level OS code or compilers is not strictly required, but highly desirable. While not strictly a requirement, preference will be given to candidates who can produce 1,000 lines of code or more per week when building prototypes. Interest and eagerness to work in a wide range of systems projects each year is highly desired. Internal candidates should have a high ratio of exceeded ratings on their annual reviews. Thanks galen

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[ANNOUNCE] Introducing Codezero
by Bahadir Balban 11 Jun '09

11 Jun '09

Hi Everyone, I would like to announce my ongoing work on a new L4 microkernel called Codezero. Codezero is a modern L4 microkernel implementation written in C. It targets embedded platforms, supports the ARM architecture, and aims to implement both virtualization and native OS components in one system. Codezero has a design and API that is similar to existing L4 microkernels such as Pistachio. The software currently comes with two services: First one is the default pager called MM0 that provides memory management capabilities with a POSIX-like API. It supports proper demand paging and implements calls such as fork, clone, execve, exit, mmap, shm. The second service is called FS0 and it implements the virtual filesystem layer. This service supports calls such as open, close, read, write, lseek, stat, fsync, etc. The software comes with a GPLv3 license, and a copyright share agreement option for contributions. The source code base is fairly clean and easy to play with. I encourage anybody interested in development to join. For more details: http://www.l4dev.org Thanks, -- Bahadir Balban

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The implementation of CPU reservation server
by Sean 08 Jun '09

08 Jun '09

Dear Now I am tracing the source code of cpu reservation server in l4/pkg/cpu_reserve directory. And I got several questions... 1. The bottom of cpu reservation server is implemented by l4_rt_add_timeslice(), l4_rt_set_period(), l4_rt_begin_strictly_periodic() functions. And these functions are defined in l4/pkg/l4sys/include/ARCH-x86/rt_sched-impl.h which calls l4_rt_generic() function. Function l4_rt_generic() is implemented by inline assembly, and it seems to call the system call "thread_schedule". Because these functions only appears in ARCH-x86 directory, do they support on ARM architecture? If not, how can I implement similar behaviors of these functions? Where can I find the document about the L4 system call API ? I can't really understand the behavior of these functions. 2. When system contains three user threads, I want to control Fiasco scheduler not to schedule one thread in these three threads during one time interval. How can I implement it? The simplest way seems to control this thread into un-running state. How can I achieve this by a supervisal server? I'm sorry for my poor English and lengthy question. I'm glad if you give me some hints or corrections. Thanks a lot! Best Regards, Sean

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The behavior of scheduler in L4Linux on ARM architecture
by Sean 21 May '09

21 May '09

Dear Now I am studying the scheduler design issue of DROPS including Fiasco and L4Linux. In the reference document, "L4Linux Porting Optimizations", it said that " In an L4Linux system two schedulers are active. One is in the L4 kernel scheduling all L4 threads including L4Linux processes. The L4 scheduler uses static priorities and schedules threads with the same priority round-robin. The other scheduler is in the Linux server, deciding which Linux process to run next. L4Linux is designed in a way that from the view of the Linux server multiple user processes can be running in the L4 system. Furthermore, the Linux scheduler can only consider those processes that are blocked in the server. Consequently, the Linux server needs to distinguish between user processes being served by the Linux server and the ones running." For the behavior of the scheduler in L4Linux, I got some questions below. 1. In L4Linux, the process/thread will map to several L4 Threads. How the scheduler in the Linux Server considers user processes in L4Linux whether to execute in L4 system ? According to the document, does L4Linux scheduler only control the user process whether block or not? 2. Based on the L4Linux source code from currently SVN, the behavior of schedule() function (kernel/sched.c line 4546) is => If next != prev, call context_switch() function => In context_switch() function (kernel/sched.c Line 2649), it calls architecture dependent function switch_to() => In switch_to() function (arch/l4/include/asm/arch-arm/system.h Line 222), it calls l4x_switch_to() function and __switch_to() function => In l4x_switch_to() function (arch/l4/kernel/arch-arm/dispatch.c Line 170), it logs the message to Trace Buffer of Fiasco and set l4x_current_process => In __switch_to() function (arch/l4/kernel/arch-arm/switch_to.S Line 5), it store the registers to CPU context of thread_info and load all regs saved previously Based on the source code analysis, it seems that when the L4Linux scheduler decide to do the context switch, the architecture dependent function __switch_to() will do the register restore and load. According to the document, I think the behavior here should set the corresponding thread status of prev and next user process to block or unblock these L4 threads. But here it does low level register restore and reload operations to change the current running process directly. It confuses me. Can anyone give me any ideas to address this? Thanks a lot! Best Regards, Sean

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