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2827 discussions

Question about RCU subsystem in Fiasco kernel.
by deng.chao1＠zte.com.cn 17 May '15

17 May '15

Hi, I find Fiasco has a implementation of RCU(Read-Copy Update)synchronization mechanism, but I did not find there was any usage of it in Fiasco kernel.. Is this implementation of RCU complete? Will there be any RCU's application in Fiasco kernel?

2 1

question about file mapping
by yang.wei9＠zte.com.cn 17 May '15

17 May '15

Hi, I create a file on tmpfs, and it read/write works fine. However, it cannot mmap, and returns EINVAL. I found the reason is that dataspace of the file is not valid. L4::Cap<L4Re::Dataspace> fds = fi->data_space() if (!fds.is_valid()) { return -EINVAL; } How to make it valid? Is there another method to do file mapping? Here is an example code snippet: ========================== const char* filename = "/tmp/testfile"; ret = mount("/", "tmp", "tmpfs", 0, 0); fd = open(filename, O_RDWR|O_CREAT); write 10K data into file addr = mmap(NULL, 4096, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0); //return -1, and errno is EINVAL -------------------------------------------------------- ZTE Information Security Notice: The information contained in this mail (and any attachment transmitted herewith) is privileged and confidential and is intended for the exclusive use of the addressee(s). If you are not an intended recipient, any disclosure, reproduction, distribution or other dissemination or use of the information contained is strictly prohibited. If you have received this mail in error, please delete it and notify us immediately.

2 1

anything wrong when call Thread::do_ipc?
by watermirror 17 May '15

17 May '15

hi. in the Thread_object::invoke, it call Thread::do_ipc like this: ct->do_ipc(f->tag(), partner, partner, have_rcv, sender, f->timeout(), f, rights); the second parameter's type is Thread*. but the Thread::do_ipc's implemention is like this: Thread::do_ipc(L4_msg_tag const &tag, bool have_send, Thread *partner, bool have_receive, Sender *sender, L4_timeout_pair t, Syscall_frame *regs, L4_fpage::Rights rights) {...} the second parameter's type is bool. is there anything wrong with the code, or i have make some mistakes?

2 1

the Thread::do_ipc's parameter
by watermirror 17 May '15

17 May '15

Hi, in the method Thread::do_ipc, there's a parameter named 'partner'.what is the 'partner' used for?

2 1

Fiasco & L4 boot performance
by Arttu Pulli 11 May '15

11 May '15

Hi, I'm working on optimizing the boot time of our Fiasco/L4Re based system. So far I've implemented some simple optimizations, like using fixed delay loop calibration value, disabling prints (is there some centralized way to disable all printing for the whole system?), and removing all unnecessary IO configurations which helped quite a bit. However, I'm pretty new to L4 and Fiasco, so I wanted to ask if you'd have some tips & tricks (no matter how arcane) on improving either the boot performance or reducing the resulting image size? My current boot time on an iMX6Q board from after U-Boot gives execution to L4 to my own L4 app is ~225 ms, and the resulting image size is 2.8 MB (1.2 MB LZO'ed). Do those numbers sound like there is anything to be gained anymore, or are those close to some maybe-known lower limits already? Regarding IO initialization, is there any way to perform some of the IO inits later on instead of when IO starts during boot time? My goal is to have my own L4 app running as fast as possible, and boot L4Linux after that. The problem is, the IO configs for the L4Linux take a lot of time, so I'd much rather invoke them at the latest possible moment. I've also removed all unnecessary modules from the modules.list configuration file, I take it that this means no unnecessary stuff is added to the image even though most everything is compiled at build time? Best regards, Arttu

2 1

Re: Testing Fiasco.OC+L4re on ODROID-X2(Exynos4412)
by Reinier Millo Sánchez 11 May '15

11 May '15

Hi Adam >> > FPU0: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard, >> > p: dbl/sngl >> > >> > KERNEL: Warning: No page-fault handler for 0xee202214, error >> > 0x94000848, pc f0039420 >> > >> >Somebody have tested Fiasco.OC+L4re on ODROID-X2 or another Exynos 4412 >> >platform? > On this platform this seems to be some pattern. However, last time I > tried it worked for me. So, hmm, could you try another compiler version > and see if it changes behavior? Maybe this gives us some hints. I'm using a linaro toolchain (gcc-linaro-arm-linux-gnueabihf-4.8-2014.03_x86_64). I have tried the arm-none-eabi toolchain in Debian repository but fails compiling the snapshot. I have made some progress trying to run FiascoOC+L4re on Odroid-X2. There are some changes that I have made: I have modified the file "l4/mk/platforms/exynos4.conf" adapting Exynos4's platform to Odroid-X2. In this case the RAM size differs (Odroid-X2 have 2Gb). In this file I have configured the UART for serial output (I'm using UART 1). PLATFORM_RAM_BASE = 0x40000000 - PLATFORM_RAM_SIZE_MB = 1024 + PLATFORM_RAM_SIZE_MB = 2047 + PLATFORM_UART_NR = 1 Booting the generated image I have detected that bootstrap's server is not using UART 1 for output. I have modified the "init" function on "l4/pkg/bootstrap/server/src/platform/exynos.cc" to use the configured UART on the platform file modified above. unsigned long uart_base; - unsigned uart_nr = 2; + unsigned uart_nr = PLATFORM_UART_NR; I have tried to compile and test the image on the Odroid-X2, but fails the execution, this is the serial output: L4 Bootstrapper Build: #18 Sat May 2 15:56:00 CDT 2015, 4.8.3 20140303 (prerelease) Scanning up to 2047 MB RAM, starting at offset 32MB Memory size is 2047MB (40000000 - bfefffff) Limiting 'RAM' region [ 40000000, bfefffff] { 7ff00000} to [ 40000000, bcffffff] { 7d000000} due to 3024 MB address limit RAM: 0000000040000000 - 00000000bcffffff: 2048000kB Total RAM: 2000MB Scanning fiasco Scanning sigma0 Scanning moe Moving up to 5 modules behind 41100000 moving module 02 { 410b4000-410e565f } -> { 411a5000-411d665f } [202336] moving module 01 { 410aa000-410b3377 } -> { 4119b000-411a4377 } [37752] moving module 00 { 41043000-410a9daf } -> { 41134000-4119adaf } [421296] moving module 04 { 41029000-410425b3 } -> { 4111a000-411335b3 } [103860] moving module 03 { 4100f000-41028493 } -> { 41100000-41119493 } [103572] Loading fiasco Loading sigma0 Loading moe find kernel info page... found kernel info page at 0x40002000 Regions of list 'regions' [ 40000000, 400000e3] { e4} Root mbi_rt [ 40001000, 40001aff] { b00} Kern fiasco [ 40002000, 40076fff] { 75000} Kern fiasco [ 40090000, 4009681b] { 681c} Sigma0 sigma0 [ 40098000, 4009e177] { 6178} Sigma0 sigma0 [ 40140000, 4018b4ab] { 4b4ac} Root moe [ 41000000, 4100e4ff] { e500} Boot bootstrap [ 41100000, 41133fff] { 34000} Root Module API Version: (87) experimental Sigma0 config ip:40090100 sp:00000000 Roottask config ip:4014020c sp:00000000 Starting kernel fiasco at 400012c8 Hello from Startup::stage2 Per_cpu_data_alloc: (orig: 0xf0063a50-0xf00644d0) Number of IRQs available at this GIC: 160 FPU0: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard, p: dbl/sngl KERNEL: Warning: No page-fault handler for 0xee202214, error 0x94000848, pc f0039420 I have been testing and changing the compiling configuration. Using the below configuration to compile Fiasco.OC, the system boots and hangs at "Calibrating timer loop...": Platform Timer -> Multi-core timer Use ExtGic -> True Execution Model -> TrustZone normal side Secure Monitor Interface -> Mobicore Enable multi processor support -> True Maximal supported number of CPUs -> 4 This is the serial output when tested the image on Odroid-X2: L4 Bootstrapper Build: #56 Tue May 5 01:08:40 CDT 2015, 4.8.3 20140303 (prerelease) Scanning up to 2047 MB RAM, starting at offset 32MB Memory size is 2047MB (40000000 - bfefffff) Limiting 'RAM' region [ 40000000, bfefffff] { 7ff00000} to [ 40000000, bcffffff] { 7d000000} due to 3024 MB address limit RAM: 0000000040000000 - 00000000bcffffff: 2048000kB Total RAM: 2000MB Scanning fiasco Scanning sigma0 Scanning moe Moving up to 5 modules behind 41100000 moving module 02 { 41090000-410c165f } -> { 41181000-411b265f } [202336] moving module 01 { 41086000-4108f377 } -> { 41177000-41180377 } [37752] moving module 00 { 41043000-4108534f } -> { 41134000-4117634f } [271184] moving module 04 { 41029000-410425b3 } -> { 4111a000-411335b3 } [103860] moving module 03 { 4100f000-41028493 } -> { 41100000-41119493 } [103572] Loading fiasco Loading sigma0 Loading moe find kernel info page... found kernel info page at 0x40002000 Regions of list 'regions' [ 40000000, 400000e3] { e4} Root mbi_rt [ 40001000, 40001aff] { b00} Kern fiasco [ 40002000, 4004efff] { 4d000} Kern fiasco [ 40090000, 4009681b] { 681c} Sigma0 sigma0 [ 40098000, 4009e177] { 6178} Sigma0 sigma0 [ 40140000, 4018b4ab] { 4b4ac} Root moe [ 41000000, 4100e4ff] { e500} Boot bootstrap [ 41100000, 41133fff] { 34000} Root Module API Version: (87) experimental Sigma0 config ip:40090100 sp:00000000 Roottask config ip:4014020c sp:00000000 Starting kernel fiasco at 400012c8 Hello from Startup::stage2 Per_cpu_data_alloc: (orig: 0xf0040110-0xf0040b18) Number of IRQs available at this GIC: 160 FPU0: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard, p: dbl/sngl Watchdog initialized SERIAL ESC: allocated IRQ 85 for serial uart Not using serial hack in slow timer handler. Welcome to Fiasco.OC (arm)! L4/Fiasco.OC arm microkernel (C) 1998-2013 TU Dresden Rev: unknown compiled with gcc 4.8.3 for Samsung Exynos [] Build: #68 Tue May 5 01:08:28 CDT 2015 Per_cpu_data_alloc: (orig: 0xf0040110-0xf0040b18) KERNEL: Warning: Buddy::alloc: Size mismatch: a08 v 1000 Allocate 2568 bytes (3KB) for CPU[4] local storage (offset=13a4ef0, 0xf13e5000-0xf13e5a08) Timer for CPU0 is at IRQ 28 Number of CPUs: 4 Calibrating timer loop... Per_cpu_data_alloc: (orig: 0xf0040110-0xf0040b18) KERNEL: Warning: Buddy::alloc: Size mismatch: a08 v 1000 Allocate 2568 bytes (3KB) for CPU[1] local storage (offset=13a6ef0, 0xf13e7000-0xf13e7a08) FPU1: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard, p: dbl/sngl Per_cpu_data_alloc: (orig: 0xf0040110-0xf0040b18) Timer for CPU1 is at IRQ 28 KERNEL: Warning: Buddy::alloc: Size mismatch: a08 v 1000 CPU[1]: goes to idle loop Allocate 2568 bytes (3KB) for CPU[2] local storage (offset=13a9ef0, 0xf13ea000-0xf13eaa08) FPU2: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard, p: dbl/sngl Per_cpu_data_alloc: (orig: 0xf0040110-0xf0040b18) Timer for CPU2 is at IRQ 28 KERNEL: Warning: Buddy::alloc: Size mismatch: a08 v 1000 CPU[2]: goes to idle loop Allocate 2568 bytes (3KB) for CPU[3] local storage (offset=13acef0, 0xf13ed000-0xf13eda08) FPU3: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard, p: dbl/sngl Timer for CPU3 is at IRQ 28 CPU[3]: goes to idle loop I think that the problem now is with the Exynos4's Timers, but i have been reviewing the implementations and it seems fine. Is there anything wrong on my configuration or somebody have any idea? Best regards -- Lic. Reinier Millo Sánchez Centro de Estudios de Informática Universidad Central "Marta Abreu" de Las Villas Carretera a Camajuaní Km 5 1/2 Santa Clara, Villa Clara, Cuba CP 54830 "antes de discutir ... respira; antes de hablar ... escucha; antes de escribir ... piensa; antes de herir ... siente; antes de rendirte ... intenta; antes de morir ... vive"

2 1

Re: Using a second UART to control a serial device
by Pflaum, Clemens 10 May '15

10 May '15

Hi L4 Hackers, Since i sadly still cant get the uart to work i have some more questions. 1. I've noticed that the offsets of all the registers in the /drivers-frst/uart/src/uart_pxa.cc are are incorrect by a multiple of 4. So if IER is defined to be at 0x01 it is actually at 0x04, respectivly the LCR which is said to be at 0x03 is actually at 0x0C. After I changed these values to reflect the allwinner A20 manual, the kernel stopped loading properly. It gets stuck on bootup at "Starting kernel...". In fact it does continue although at a pace of one character every 5 to 6 minutes. So after 30mins i had "L4 Bootstra" in the next line. My assumption is that my UART0 from which i run the console on my linux pc actually uses the uart_pxa driver with the incorrect register offset and it works for it. By changing the registers I somehow break my UART0. If I'm correct then I should be able to find the routine which the kernel uses to initilize UART0, to help me understand how to get UART3 to work. Sadly I couldn't find anything alike. 2.So i went on by writing a new uart_16550bananapi.cc with changed registers. It did infact solve the kernel not starting issue. I can now access and write to all of the uart registers... apart from the Line Control Register(LCR). It starts off with 0x03 written to it although it has a default of 0x00(in the a20 manual) as soon as i write 0x00 to it my console starts throwing out seemingly random chars: This code in the uart startup() function: scratch = _regs->read<unsigned char>(LCR); printf("\ncurrent LCR: %#010x\n", scratch); printf("Setting LCR to 0\n"); printf("This gets overritten\n"); _regs->write<unsigned char>(LCR, 0); /* clear line control register */ printf("It worked\n"); gives me this outpot on console: Maestro | Maestro | current LCR: 0x00000003 Maestro | Setting LCR to 0 Maese|iw�k�{m{[e|{m{[e|pp`'br�l�z{mos�pppppn{m{[e��r|{m{[e p�ot[ lLzppppp{m{[e|pq`�rppppp{m{ێm[e|pqlNzppppv{m{[e|pq`�rppppp{m{ێm[e q The same thing happens if i write 0x80 to it to add the DLAB bit that i need to access the two Divisor Latch registers to initilize the Baudrate for the first time. The 0x03 in LCR means that i run my Uart in 8N1 mode setting which my UART0 console is running aswell. Setting it to 0 means to run 5N1. So I assume for some reason it might somehow change my UART0 settings if i write to UART3 LCR reg. But the same error occurs if i write 0x83 to it to leave 8N1 on and set the DLAB bit, so that cant be the case can it? Without setting Baudrate however i obviously cant hope for UART3 to work. Thanks for any answers in advance, Clemens

3 8

about Ram_quota
by watermirror 08 May '15

08 May '15

hi, what is Ram_quota used for?

2 1

Static_object::construct
by watermirror 08 May '15

08 May '15

hi, template< typename T > class Static_object { public: .... template< typename... A > T *construct(A&&... args) { return new (_i) T(cxx::forward<A>(args)...); } ... }; this template class is defined in fiasco/src/types.h, what does the method 'construct' mean? i have tried to move this class to eclipse cdt project, but it can not be compiled correctly. how does this class be compiled in fiasco?

2 1

Testing Fiasco.OC+L4re on ODROID-X2(Exynos4412)
by Reinier Millo Sánchez 04 May '15

04 May '15

Hi comunity I'm trying to test the hello application on the ODROID-X2(Exynos4412) board. I'm using the Fiasco.OC+L4re snapshot(l4re-snapshot-2014092821). I have configured and compiled Fiasco.OC with support to Samsung Exynos4412: export SYSTEM_TARGET=arm-linux-gnueabihf- make BUILDDIR=build-foc make menuconfig make -j16 After that, I have compiled the entire L4re for armv7a (SamsungExynos4) make B=build-l4re make O=build-l4re ARCH=arm SYSTEM_TARGET=arm-linux-gnueabihf- menuconfig make O=build-l4re ARCH=arm SYSTEM_TARGET=arm-linux-gnueabihf- -j16 To generate the raw image have modified the conf/Makeconf.boot to set the Fiasco.OC build path and executed: make O=build-l4re ARCH=arm SYSTEM_TARGET=arm-linux-gnueabihf- rawimage E=hello I have copied the generated image into the SD card and tried to boot from u-boot: fatload mmc 0:1 0x41000000 hello.raw bootm 0x41000000 The system starts but stops execution. This is the serial output: Partition1: Start Address(0xc00), Size(0x40400) reading hello.raw 942080 bytes read Boot with zImage Starting kernel ... Hello from Startup::stage2 Per_cpu_data_alloc: (orig: 0xf0063a50-0xf00644d0) Number of IRQs available at this GIC: 160 FPU0: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard, p: dbl/sngl KERNEL: Warning: No page-fault handler for 0xee202214, error 0x94000848, pc f0039420 Somebody have tested Fiasco.OC+L4re on ODROID-X2 or another Exynos 4412 platform? Best regards -- Lic. Reinier Millo Sánchez Centro de Estudios de Informática Universidad Central "Marta Abreu" de Las Villas Carretera a Camajuaní Km 5 1/2 Santa Clara, Villa Clara, Cuba CP 54830 "antes de discutir ... respira; antes de hablar ... escucha; antes de escribir ... piensa; antes de herir ... siente; antes de rendirte ... intenta; antes de morir ... vive"

2 1

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