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IPC stream magic
by teclis High Elf 11 Apr '15

11 Apr '15

I have a complex nested structure that looks something like this: typedef struct struct_A { int i; struct struct_B[5]; int j; } using an IPC stream I do: struct_A a; ios.put(a); and then in the server process I do: struct_A b; ios.get(b); ( ios is a L4::Ipc::Iostream ) and magically my complex nested structure reappears with all the data intact in the server process running in another address space. As the IPC Streams are not well documented would someone be able to explain to me how my complex nested structure got automatically marshalled in the client and unmarshalled in the server process?

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Re: ARM with Qemu
by Nicolas VARONA 09 Apr '15

09 Apr '15

Hi, Thanks for your answer and your help. >Could also be the uart issue? But entering jdb always works for me. Even if I can't give inputs to the bare metal application on Qemu, I can also enter into the JDB. Is that mean that all interruptions are well handled? So the uart issue seems more probable. >Which kind of panic? I firstly tested my L4linux on Qemu for the Zinq board and the boot finishes well (with the problem of inputs that I told you before). Nonetheless, with the same image on the board, I have this message: [...] Freeing unused kernel memory: 116K (0230f000 - 0232c000) potentially unexpected fatal signal 11. CPU: 0 PID: 1 Comm: init Not tainted 3.16.0-l4 #152 task: 05c23ac0 ti: 05c26000 task.ti: 05c26000 PC is at 0x0 LR is at 0x0 pc : [<00000000>] lr : [<00000000>] psr: 60000010 sp : bf73cef0 ip : 00000000 fp : 00000000 r10: 00000000 r9 : 00000000 r8 : 00000000 r7 : 00000000 r6 : 00000000 r5 : 00000000 r4 : 00000000 r3 : 0000c50c r2 : 00000000 r1 : 00000000 r0 : 00000000 vcpu: b3000c00 vcpu-state: 00000001 Flags: nZCv IRQs on FIQs on Mode USER_32 ISA ARM Segment user CPU: 0 PID: 1 Comm: init Not tainted 3.16.0-l4 #152 [<0200c9c8>] (unwind_backtrace) from [<020055e8>] (show_stack+0x10/0x14) [<020055e8>] (show_stack) from [<0202844c>] (get_signal_to_deliver+0x204/0x490) [<0202844c>] (get_signal_to_deliver) from [<02006be8>] (do_signal+0x114/0x448) [<02006be8>] (do_signal) from [<0200a210>] (l4x_vcpu_entry_c+0xa94/0x1da8) [<0200a210>] (l4x_vcpu_entry_c) from [<00000000>] ( (null)) Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b CPU: 0 PID: 1 Comm: init Not tainted 3.16.0-l4 #152 [<0200c9c8>] (unwind_backtrace) from [<020055e8>] (show_stack+0x10/0x14) [<020055e8>] (show_stack) from [<022441a4>] (panic+0x7c/0x1e0) [<022441a4>] (panic) from [<0201e6a8>] (do_exit+0x708/0x7a0) [<0201e6a8>] (do_exit) from [<0201e80c>] (do_group_exit+0x3c/0x9c) [<0201e80c>] (do_group_exit) from [<02028390>] (get_signal_to_deliver+0x148/0x490) [<02028390>] (get_signal_to_deliver) from [<02006be8>] (do_signal+0x114/0x448) [<02006be8>] (do_signal) from [<0200a210>] (l4x_vcpu_entry_c+0xa94/0x1da8) [<0200a210>] (l4x_vcpu_entry_c) from [<00000000>] ( (null)) ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b panic: going to sleep forever, bye l4linux | panic: going to sleep forever, bye Thanks in advance for your help, Nicolas >Hi, > >On Mon Mar 02, 2015 at 15:10:04 +0100, Nicolas VARONA wrote: >> I am trying to set up a simulator with Qemu and l4linux ARM to >> simulate the Zynq board. I have successfully compiled Fiasco and L4 >> with the tool chain "arm-linux-gnueabi-gcc". I succeeded to launch >> l4linux but I have no input on l4linux when it's running on Qemu. >> Nevertheless, the fiasco jdb can be invoked. After reading the mailing >> list I changed the hello world program to take inputs and tried a bare >> metal application with l4re with the same result (I didn't modify the >module list). >> >> So, I tried to do the same thing with the board and I have inputs with >> the l4 bare metal application > >So I looked a bit at this and it seems to me that there's something strange >with uart rx in Qemu, or at least which only shows up in Qemu. >I need to investigate that further. > >> and a kernel panic for the l4linux. > >Which kind of panic? > >> I boot >> with the uboot image on it. Nonetheless, using uImage for qemu doesn't >> change anything: >> >> ./qemu-system-arm -M arm-generic-fdt-plnx -m 512M -kernel >> /path/bootstrap.uimage -dtb /path/devicetree.dtb -serial mon:stdio >> >> I tried to compile the u-boot from Xilinx and Qemu freezes when I >> launch the l4 application. > >Could also be the uart issue? But entering jdb always works for me. > >> To be sure I have done things right, I also tried the modified hello >> world program on x86 intel and it works well. Then I launched a >> Petalinux with Qemu and a uImage with uboot and it works. >> >> My Qemu is from Xilinx: QEMU emulator version 2.0.50 > >Oh, good to know. I tried the normal one.

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Question about L4/Fiasco running the kernel with interrupts disable
by deng.chao1＠zte.com.cn 08 Apr '15

08 Apr '15

Hi all， I have read the wikipedia website of L4 kernel(http://en.wikipedia.org/wiki/L4_microkernel_family), it says that L4/Fiasco was designed "fully preemptible to achieve a low interrupt latency " at first, however "the complexities of a fully preemptible design resulted in later versions of Fiasco to return to the traditional L4 approach of running the kernel with interrupts disabled ". I am very interested in the kernel's interrupt latency. I have check the latest versions of Fiasco kernel in running, and it keeps interrupts disabled indeed. So I wonder whether there was any early version of L4/Fiasco which supported fully preemptible? Or was there any article talked about this ? Thanks！

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Question about L4/Fiasco running the kernel with interrupts disable
by cui.yunfeng＠zte.com.cn 08 Apr '15

08 Apr '15

Hi all， I have read the wikipedia website of L4 kernel(http://en.wikipedia.org/wiki/L4_microkernel_family), it says that L4/Fiasco was designed "fully preemptible to achieve a low interrupt latency " at first, however "the complexities of a fully preemptible design resulted in later versions of Fiasco to return to the traditional L4 approach of running the kernel with interrupts disabled ". I am very interested in the kernel's interrupt latency. I have check the latest versions of Fiasco kernel in running, and it keeps interrupts disabled indeed. So I wonder whether there was any early version of L4/Fiasco which supported fully preemptible? Or was there any article talked about this ? Thanks！

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about ".initcall.text" and ".initcall.data"
by 水镜 07 Apr '15

07 Apr '15

hi ,there are ".initcall.data" and ".initcall.data" in the kernel.ia32.ld, what are these two sections for?

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Microkernel Meetup
by Björn Döbel 04 Apr '15

04 Apr '15

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi all, it is time for another Microkernel Meetup! As many regulars seem to be travelling mid/late April, I suggest we go to B'liebig, Liebigstraße 24 http://b-liebig.de/ either on April 7 or on April 9. Please participate in the Dudle so I can reserve a table: https://dudle.inf.tu-dresden.de/uks0415/ Also, please distribute this email to anyone you think might be interested in coming. Cheers, Bjoern -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iEYEARECAAYFAlUSfX0ACgkQP5ijxgQLUNmsjQCeP07bdeWG7cANxiaT2U1DqT+N 9+EAmQH4tcieJL4S1VAiOkOCJaGQqsJG =XTl6 -----END PGP SIGNATURE-----

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Denial of service in microkernel
by Gayathri Nagarajan 01 Apr '15

01 Apr '15

I executed fork bomb(a process continually replicates itself to deplete the system resources), a denial of service attack in Linux kernel and the kernel got crashed. This is because of the depletion of resources and starvation. But, upon executing the same application in L4linux under the Fiasco.oc with L4re microkernel architecture, no crashing occurs. What is the reason behind this stability? How does the microkernel(Fiasco.OC) handle the system calls ? # Code for the fork bomb application : #include<unistd.h> int main(void) { while(1) fork(); //system call }

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Fiasco testcase And L4RE API
by cui.yunfeng＠zte.com.cn 31 Mar '15

31 Mar '15

hi L4 hacker: I am learning Fiasco, there are some question about Fiasco and L4RE. Is there unit test case (such as TDD test case) on development of Fiasco? How to get the unit test case? Is there document about L4RE API interface? I want to compare the L4RE POSIX interface and Linux POSIX interface. Thanks a lot.

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(no subject)
by zhou.li9＠zte.com.cn 31 Mar '15

31 Mar '15

Now I want to debug Fiasco.OC kernel with JDB, the version of Fiasco.OC is 2014092821. Mentioned in a jdb.pdf document section 4.14, need to use RMGR to load the symbol table, but I did not find any manpage on the RMGR. where is the manpage or how to load the symbol table? -------------------------------------------------------- ZTE Information Security Notice: The information contained in this mail (and any attachment transmitted herewith) is privileged and confidential and is intended for the exclusive use of the addressee(s). If you are not an intended recipient, any disclosure, reproduction, distribution or other dissemination or use of the information contained is strictly prohibited. If you have received this mail in error, please delete it and notify us immediately.

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L4 and Lua interaction
by daniel krefft 30 Mar '15

30 Mar '15

Hi there, please can you give us a short overview about the L4 and Lua interaction/integration? The most important aspect is to understand how Lua-Scripts are used to create/manage the VBus. In particular from which module/component are the Lua-Scripts read/processed (NED, SIGMA0)? We found an example about Ankh (ankh.vbus, aw.lua, lwip.lua). Maybe it is possible to exemplify it via Ankh. Regards, Daniel -- Mit freundlichen Grüßen Daniel Krefft ***************************************************************** * Daniel Krefft M.Sc. * * T: +49-89-289-18791 * * * Technische Universitaet Muenchen * Fakultaet fuer Informatik - F13 (Prof. Baumgarten) * Boltzmannstr. 3 * D-85748 Garching bei Muenchen * Germany *****************************************************************

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