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Build system
by teclis High Elf 14 Aug '14

14 Aug '14

If I execute this command from the l4 build directory: make E=hello S=bootstrap In which Makefile or script is the S= processed (its a bit of a difficult thing to grep for :) thanks

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Accessing dbg_info()->dbg_id() for threads in ready queue class
by Valentin Hauner 13 Aug '14

13 Aug '14

Hi, how can I access the identificator used in JDB's thread list in the enqueue method of my ready queue class? Following code snippet does not work: > include "thread.h" > [...] > Ready_queue_edf<E>::enqueue(E *i, bool) { > printf("%d", static_cast<Thread*>(i->context())->dbg_info()->dbg_id()); } It results in various compiler errors: > [...] > ./kernel/fiasco/src/kern/irq.cpp:504:11: error: ‘class Thread’ has no member named ‘home_cpu’ > ./kernel/fiasco/src/kern/irq.cpp:505:15: error: ‘class Thread’ has no member named ‘drq’ > [...] > ./kernel/fiasco/src/kern/tcboffset_in.h:11:3: error: ‘class Thread’ has no member named ‘_caller’ > ./kernel/fiasco/src/kern/tcboffset_in.h:14:3: error: ‘class Thread’ has no member named ‘_timeout’ What else do I have to include that it works? Best regards, Valentin

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Mapping memory into process address space
by Noah Zentzis 13 Aug '14

13 Aug '14

I'm trying to launch a new process (without libloader) and I'm having trouble mapping memory to it. I've found the prog_attach_ds and prog_reserve_utcb_area methods in libloader and ned, but I'm not sure where they're getting the memory to assign or the region map for the task. Can I just do something like: L4Re::Util::Cap<L4Re::Dataspace> stack; L4Re::Env::mem_alloc()->alloc(0x10000, stack); or are there special steps I need to take when I want to give another process access to the same memory? Thanks! - Noah Zentzis

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Question about IPI interrupt handler
by Yuxin Ren 11 Aug '14

11 Aug '14

Hi All, I cannot understand the logic of the IPI interrupt handler very well. I hope someone can help me. Thanks a lot. I am using intel IA32 multi core cpu. My scenario is one client and one server thread on different core. Client sends simple data-only IPC to the server. 1. The function Thread::handle_remote_requests_irq is the IPI interrupt handler, right? So it is running within the interrupt context? If so, 2. In this function, the variable "c" is set to the current Context. On the server core, when the server is blocked(waiting for IPC), what is current Context? The server thread or the idle thread? I have no other threads in the user level, and I assume there are no background threads in the kernel or L4Re. In addition, I guess each thread associates with a Context. If my assumptions are right and that current Context is idle thread, 3. At the last of this function, it calls c->handle_drq(). But when does the server thread's handle_drq() is called? 4. In what situation, the variable "resched" will be set to true? When it is true, 5. c->schedule() will be called, does it mean that we can switch to another thread in the interrupt context? It cannot make sense to me. Thanks again. Best, Yuxin

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how to get or initialize clock in L4Linux
by Yunchuan Geng 08 Aug '14

08 Aug '14

Hi, L4hackers, I am implementing I2C drivers from native linux to L4Linux. I am using Freescale iMX6Q SD board. Kernel version 3.14 in ./drivers/i2c/busses/i2c-imx.c, function i2c_imx_probe(), devm_clk_get() is called. And fails at here. I understand that clock are initialized from function "__init imx6q_clocks_init()". I managed to compile and call the imx6q_clocks_init() function from L4Linux, but encountered many problem. The question is, Is it necessary to initialize clocks in L4Linux and how? Thanks in advance? -Yunchuan

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strange response time question
by Yuxin Ren 06 Aug '14

06 Aug '14

Hi All, Now I am testing the response time in Fiasco, especially for the worse case. The results are strange. The worse case result are always around 2us. I have filtered out the timer interrupt, so I cannot understand what happened. I am using intel IA32 multi core cpu. Do you have any idea about what can cause the 2us delay? Thank you so much. Yuxin

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response time in Fiasco
by Yuxin Ren 05 Aug '14

05 Aug '14

Hi All, Are there any papers or documentation talking about response time in Fiasco? I think this is an important aspect in Fiasco as it is designed for real time. Thank you. Yuxin

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DDE-Kit
by Korbinian Ederer 05 Aug '14

05 Aug '14

Hello, I'm searching for some Informations about using the dde-kit. My goal is to use the SocketCan driver from Linux eith the l4re on an ARM BeagleBone Black (Omap3x). The Manual at http://os.inf.tu-dresden.de/ddekit/ did not work because of missing l4/sys/cache.h After some searching I discovered a copy of dde also in the fiasco snapshot in l4/pkg/dde/ but have no idea of how to use it. I would be very helpfull to get some advice about usefull documentation or some hints about the usage of dde Thanks a lot Korbinian Ederer

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Do L4 Linux lack source code about Freescale i.MX6 Quad ?
by Taeung 04 Aug '14

04 Aug '14

Hello , L4 hackers I always appreciate L4 hackers. I've succeed boot "helloworld + L4/Fiasco" on Freescale i.MX6q_sabre_sd. So, I've try to build L4 linux (|Repository : svn co http://svn.tudos.org/repos/oc/l4linux/trunk l4linux|). I've configured for build L4 Linux such as.. ====================================================== System type ---> ARM system type (Allow multiple platforms to be selected) Multiple platform selection ---> ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait) Build type Freescale i.MX family Freescale i.MX support ---> i.MX6 Quad/DualLite support ====================================================== But I've meet errors even so often. such as .. 1. ERROR: CONFIG_ARM_PATCH_PHYS_VIRT must not be enabled. => So, I've force to change CONFIG_ARM_PATCH_PHYS_VIRT=y to =n . 2. irq.c:16:26: error: 'L4X_NR_IRQS_V_DYN' undeclared here irq.c:46:14: error: 'L4X_IRQS_V_DYN_BASE' undeclared and irq.c:48:14: error: 'NR_IRQS_HW' undeclared => So, I've included "#include <asm/generic/irq-vectors.h>" and "#include <asm/mach-arm/generic/mach/irqs.h>". 3. l4.c:57:13: error: 'L4X_IRQS_V_STATIC_BASE' undeclared ...etc. => So, I've included "#include <asm/generic/irq-vectors.h>" and "#include <asm/mach-arm/generic/mach/irqs.h>". 4. drivers/built-in.o: In function `clk_disable': clk.c:867: multiple definition of `clk_disable' arch/l4/built-in.o:/home/taeung/workspace/l4linux/arch/l4/kernel/arch-arm/l4.c:73: first defined here drivers/built-in.o: In function `clk_enable': clk.c:919: multiple definition of `clk_enable' arch/l4/built-in.o:/home/taeung/workspace/l4linux/arch/l4/kernel/arch-arm/l4.c:65: first defined here make[1]: *** [vmlinux] Error 1 make: *** [sub-make] Error 2 => So, I delete this lines in l4linux/drivers/clk/clk.c. 7. undefined reference to `__pv_phys_offset' from signal.c , init.c, mm.h ....etc. My question is.... Is it's problem that my config is wrong or l4 linux lack source code about Freescale i.MX6 Quad ? * Refer to > /home/taeung/workspace/l4linux/arch/l4/kernel/*irq.c* /home/taeung/workspace/l4linux/arch/l4/include/asm/generic/*irq-vectors.h* /home/taeung/workspace/l4linux/arch/l4/kernel/*pm.c */home/taeung/workspace/l4linux/arch/l4/kernel/arch-arm/*l4.c** */home/taeung/workspace/l4linux/arch/l4/l4lxlib/generic/*irq_gen.c* /home/taeung/workspace/l4linux/drivers/clk/*clk.c */home/taeung/workspace/l4linux/arch/l4/kernel/arch-arm/*signal.c */home/taeung/workspace/l4linux/arch/l4/mm/arch-arm/*init.c */home/taeung/workspace/l4linux/include/linux/*mm.h *

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seL4 boot issue
by Jorge Ventura 04 Aug '14

04 Aug '14

I am trying to boot seL4 on beaglebone white. I have an initial code just to configure the DDR2 memory at range 0x80000000-0xbfffffff. As we can see below, the start address is the virtual address 0xf0000000 but at this point I have no MMU configured. I was thinking that the segment .boot should be the code to prepare all details about MMU/D-CACHE/I-CACHE but it's not what gdb is understanding based in the elf header. Someone could explain to me how to boot this kernel; what do I have to consider. I guess that beaglebone is not supported but this is exactly my goal, to make seL4 boot on beaglebone. Any help or suggestion is very welcome. Sincerely, Jorge Ventura (gdb) load kernel.elf > Loading section .boot, size 0x10000 lma 0x80000000 > Loading section .text, size 0xf1ec lma 0x80010000 > Loading section .text.unlikely, size 0xd98 lma 0x8001f1ec > Loading section .rodata, size 0x4170 lma 0x8001ff84 > Loading section .data, size 0x8 lma 0x800240f4 > Start address 0xf0000000, load size 147708 > Transfer rate: 319 KB/sec, 3787 bytes/write. > (gdb) monitor poll > background polling: on > TAP: am335x.dap (enabled) > target state: halted > target halted in ARM state due to debug-request, current mode: System > cpsr: 0x6000019f pc: 0xf0000000 > MMU: disabled, D-Cache: disabled, I-Cache: disabled >

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