hello:
Recently, I consider implementation heritical scheduler on top of the l4
microkernel, But we meet a problem, the Pistachio handled the interrupt in
microkernel internal, In that time, I remember a project in TU-Dresden is
build on top of microkernel, But it`s implementation in the old l4
interface, just like the Hazelnut that not handled the interrupt (?), The
suitation is some microkernel abstract the interrupt and some microkernel
not abstract the interrupt.
Can we …
[View More]implementation a real time soft mechanism with interrupt
abstracted microkernel, the real time ipc, feature as:
interrupt generated then a ipc send to handler and switch to the handler
at once
Neil
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Hi,
it's quite some time since I last had a look at L4 and a lot
seems to have happened since then. As I'm planning to use a
L4-derived microkernel as basis for a research project here
at Marburg University, I have some questions for the experts...
The currently maintained L4-compatible microkernels seem to be
Fiasco (Dresden) and L4KA::Hazelnut/Pistachio (Karlsruhe). Is
there a document describing the differences/compatibility between
the various versions, probably comparing these …
[View More]implementations
to the original L4 kernel?
The platform for my project will probably be a AMD "Hammer"-based
system (e.g. Athlon 64 or Opteron). Is there already work underway
to run Fiasco or L4KA in 64-bit mode on the x86-64 CPUs? If not,
I'm thinking about starting an effort to port one of the kernels
(based on the x86-32 version). Which do you think would be most
appropriate?
Btw., the squirrel on the L4KA web pages is quite cute ;-) - is there a
high-res bitmap or vector graphics version of the logo available?
My last question concerns L4Linux. The most recent version seems
to be based on kernel 2.2.25. Are there any plans to adapt a
more recent Linux kernel version, like 2.4 or the upcoming 2.6,
as a L4 personality? (I'm aware that this might involve a lot of
work...)
Best regards,
Michael
--
Dipl.-Ing. Michael Engel - mengel(a)informatik.uni-marburg.de
Philipps-Universit=E4t Marburg - FB Mathematik und Informatik
Hans-Meerwein-Str. - 35032 Marburg
Tel. 06421 / 28 21562 - Fax: 06421 / 28 21573
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Hello L4 hackers,
The Fiasco Team is pleased to announce version 1.1 of the Fiasco L4
microkernel developed at the University of Technology, Dresden and
released under the GNU General Public License (GPL).
This Fiasco release is mostly a bugfix release. Among the new features added
in version 1.1 is support for the ARM processor architecture, the integration
of the powerful Fiasco kernel debugger (JDB) into the Fiasco-UX usermode
kernel and a completely revised "tagged TLB" emulation (also …
[View More]known as small
address spaces). For a more verbose list of changes since the last release
see the CHANGES file.
The Fiasco microkernel currently supports the stable version V.2 and the
experimental version X.0 of the L4 interface specification and runs on x86
(i486 and above) and ARM SA1110 CPUs. The included Fiasco-UX port runs on
any x86-based Linux system as a normal usermode application.
For further information please visit the Fiasco homepage at:
http://os.inf.tu-dresden.de/fiasco/
Happy hacking,
The Fiasco Team
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Thanks!! I'm just getting into this L4 / Hurd game. My main concern isn't
efficiency -- I leave the speed issues to the folks who give us a 2X clock
frequency boost every 18 months. :) My concerns are correctness and
stability of the OS, and various project management issues like
predictability and stability of dates, interfaces and specifications,
production of accurate and usable documentation, etc. I'm by no stretch of
the imagination a competent C++ programmer; I can just barely read C++ …
[View More]once
the object-oriented features show up.
In my trolling about, I discovered that the Fiasco folks have put some
effort into "correctness proofs" of Fiasco. See the Vfiasco site
http://os.inf.tu-dresden.de/vfiasco/
How difficult would it be to shift this effort from Fiasco to Pistachio? How
difficult would it be to port DROPS and friends
http://os.inf.tu-dresden.de/drops/
from Fiasco to Pistachio? I'm interested in both tracks -- a real-time
operating system and a general-purpose Linux-like desktop and server system.
"One OS to rule them all ..." :)
--
M. Edward (Ed) Borasky
mailto:znmeb@borasky-research.net
http://www.borasky-research.net
"Suppose that tonight, while you sleep, a miracle happens - you wake up
tomorrow with what you have longed for! How will you discover that a miracle
happened? How will your loved ones? What will be different? What will you
notice? What do you need to explode into tomorrow with grace, power, love,
passion and confidence?" -- L. Michael Hall, PhD
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Hello l4-hackers,
I run my small program as root task on top of Pistachio 0.3 microkernel
and receive some errors when it run.
All works fine, but when in KDB i try to use change verbose level of
sigma0 once and again (about 5-6 times) I receive Assertion:
Assertion !tcb->queue_state.is_set(queue_state_t::ready) failed in
file /home/tosha/pistachio-0.3/kernel/include/api/v4/schedule.h,
line 296 (fn=f010099b2)
Can you explain me where is the problem ?
Code:
#include …
[View More]<l4io.h>
#include <l4/kip.h>
#include <l4/ipc.h>
#include <l4/message.h>
#include <l4/kdebug.h>
#include <l4/thread.h>
int main (void)
{
printf("Myself: %x\n", L4_Myself().raw);
L4_Msg_t msg;
L4_ThreadId_t tid;
tid = L4_Pager();
L4_MsgClear(&msg);
L4_MsgAppendWord(&msg, 1);
L4_MsgAppendWord(&msg, 9);
L4_Set_Label(&msg.tag, -1001<<4);
L4_MsgLoad(&msg);
L4_Send(tid);
printf("aaa\n");
L4_MsgClear(&msg);
L4_MsgAppendWord(&msg, 1);
L4_MsgAppendWord(&msg, 9);
L4_Set_Label(&msg.tag, -1001<<4);
L4_MsgLoad(&msg);
L4_Send(tid);
while(true)
{
printf("root\n");
L4_KDB_Enter("enter kdb");
}
}
--
Best regards,
Anton mailto:cyberspas@narod.ru
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