April 2015 - l4-hackers - example.com Site

Graphical desktop, l4con, mag
by teclis High Elf 02 Jun '17

02 Jun '17

Guten Tag, I've got the Hello app runing with fiasco and l4re in qemu, how do I get the graphical UI and console running that I see on the screen shots page? Do I need to use l4con and mag? I don't see an entry with l4con in modules.list. danke * <http://german.about.com/library/media/Audio/gutentag.wav>*

6 15

libfs/ FUSE on L4Re
by Stark, Josef 31 May '17

31 May '17

Hello, yesterday I came across a very interesting paper titled "Porting FUSE to L4Re", accessible here: http://os.inf.tu-dresden.de/papers_ps/pester-beleg.pdf For porting FUSE, the author uses a library called "libfs" which provides filesystem request forwarding and processing, if I understood correctly. It reads as if libfs is already included in L4Re. However, I couldn't find neither FUSE nor libfs in the current L4Re snapshot. Are they by any chance publicly available somewhere else, or are both not to be published? Cheers, Josef

4 7

TrustZone example on i.MX6
by Markku Ahvenjärvi 07 Jul '15

07 Jul '15

Hello hackers, I'm trying to run Fiasco.OC in secure world and Linux in non-secure world on i.MX6Q. For this I'm using the TrustZone example (pkg/examples/sys/vm-tz). To secure world I have given 128MB RAM starting from 0x10000000 and I modified the example to give NS world 256MB starting from 0x20000000. I've replaced atags with dtb of my board and it is copied to NS side like kernel and initrd. At first I encountered runtime exception, which I fixed by implementing following to arm_em_tz builds Thread::arch_ext_vcpu_enabled() { return true; } Now I'm having problems at early stages of NS boot, where Linux kernel is checking for the dtb magic. The code loads the dtb magic from the address I'm giving in r2 register (0x21000000), but the magic value usually have one byte or all of them incorrect. I've used JDB to dump the area of dtb after hitting that error and it shows the dtb magic properly. So for some reason the NS-world gets mangled value. Any idea what might be causing this? Thanks, Markku

5 29

Re: Using a second UART to control a serial device
by Pflaum, Clemens 10 May '15

10 May '15

Hi L4 Hackers, Since i sadly still cant get the uart to work i have some more questions. 1. I've noticed that the offsets of all the registers in the /drivers-frst/uart/src/uart_pxa.cc are are incorrect by a multiple of 4. So if IER is defined to be at 0x01 it is actually at 0x04, respectivly the LCR which is said to be at 0x03 is actually at 0x0C. After I changed these values to reflect the allwinner A20 manual, the kernel stopped loading properly. It gets stuck on bootup at "Starting kernel...". In fact it does continue although at a pace of one character every 5 to 6 minutes. So after 30mins i had "L4 Bootstra" in the next line. My assumption is that my UART0 from which i run the console on my linux pc actually uses the uart_pxa driver with the incorrect register offset and it works for it. By changing the registers I somehow break my UART0. If I'm correct then I should be able to find the routine which the kernel uses to initilize UART0, to help me understand how to get UART3 to work. Sadly I couldn't find anything alike. 2.So i went on by writing a new uart_16550bananapi.cc with changed registers. It did infact solve the kernel not starting issue. I can now access and write to all of the uart registers... apart from the Line Control Register(LCR). It starts off with 0x03 written to it although it has a default of 0x00(in the a20 manual) as soon as i write 0x00 to it my console starts throwing out seemingly random chars: This code in the uart startup() function: scratch = _regs->read<unsigned char>(LCR); printf("\ncurrent LCR: %#010x\n", scratch); printf("Setting LCR to 0\n"); printf("This gets overritten\n"); _regs->write<unsigned char>(LCR, 0); /* clear line control register */ printf("It worked\n"); gives me this outpot on console: Maestro | Maestro | current LCR: 0x00000003 Maestro | Setting LCR to 0 Maese|iw�k�{m{[e|{m{[e|pp`'br�l�z{mos�pppppn{m{[e��r|{m{[e p�ot[ lLzppppp{m{[e|pq`�rppppp{m{ێm[e|pqlNzppppv{m{[e|pq`�rppppp{m{ێm[e q The same thing happens if i write 0x80 to it to add the DLAB bit that i need to access the two Divisor Latch registers to initilize the Baudrate for the first time. The 0x03 in LCR means that i run my Uart in 8N1 mode setting which my UART0 console is running aswell. Setting it to 0 means to run 5N1. So I assume for some reason it might somehow change my UART0 settings if i write to UART3 LCR reg. But the same error occurs if i write 0x83 to it to leave 8N1 on and set the DLAB bit, so that cant be the case can it? Without setting Baudrate however i obviously cant hope for UART3 to work. Thanks for any answers in advance, Clemens

3 8

Experimenting the vm-tz example on the Freescale i.mx6 SDB
by Mahdi Aichouch 04 May '15

04 May '15

Hello, I am trying to experiment the "vm-tz" example on the Freescale i.mx6 SDB board. At first, my goal is to understand the example, thus I am interested in running a simple test kernel instead of a full linux kernel. Specifically, I am trying to reproduce the experimentation of the article related to the trustzone implementation on Fiasco.OC L4re, "ARM Trustzone as a Virtualization Technique in Embedded Systems". In particular, it is mentioned in the article at the "Implementation" paragraph that "Multiplexing two or more OS is supported by our design." I would like to investigate this point. I created a new entry to generate the vm-tz binary. I added the following entry to the "src/l4/conf/modules.list" file : entry tz_vm roottask moe --init=rom/vm-tz module l4re module vm-tz Is my configuration entry correct, is there any missing modules that are required by the example? I tested the binary on the board using tftp, and I obtained the following results: L4 Bootstrapper Build: #12 Tue Mar 17 12:10:02 CET 2015, 4.8.3 20140320 (prerelease) Scanning up to 1024 MB RAM, starting at offset 32MB Memory size is 1024MB (10000000 - 4fffffff) RAM: 0000000010000000 - 000000004fffffff: 1048576kB Total RAM: 1024MB Scanning fiasco Scanning sigma0 Scanning moe Moving up to 5 modules behind 11100000 moving module 02 { 110a5000-110de63f } -> { 11195000-111ce63f } [235072] moving module 01 { 1109b000-110a438b } -> { 1118b000-1119438b } [37772] moving module 00 { 11044000-1109a0c7 } -> { 11134000-1118a0c7 } [352456] moving module 04 { 1102a000-11043597 } -> { 1111a000-11133597 } [103832] moving module 03 { 11010000-11029473 } -> { 11100000-11119473 } [103540] Loading fiasco Loading sigma0 Loading moe find kernel info page... found kernel info page at 0x10002000 Regions of list 'regions' [ 10000000, 100000e3] { e4} Root mbi_rt [ 10001000, 10001aff] { b00} Kern fiasco [ 10002000, 10062fff] { 61000} Kern fiasco [ 10090000, 10096edf] { 6ee0} Sigma0 sigma0 [ 10098000, 1009e177] { 6178} Sigma0 sigma0 [ 10140000, 10171d77] { 31d78} Root moe [ 10178000, 101934ab] { 1b4ac} Root moe [ 11000000, 1100f4ff] { f500} Boot bootstrap [ 11100000, 11133fff] { 34000} Root Module API Version: (87) experimental Sigma0 config ip:10090100 sp:00000000 Roottask config ip:10140260 sp:00000000 Starting kernel fiasco at 100012c8 Number of IRQs available at this GIC: 160 FPU0: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard, p: dbl/sngl L2: ID=410000c7 Type=9e340340 Aux=02070000 WMask=ffff S=0 L2: Type L2C-310 Size = 1024kB Ways=16 Waysize=64 SERIAL ESC: allocated IRQ 58 for serial uart Not using serial hack in slow timer handler. Welcome to Fiasco.OC (arm)! L4/Fiasco.OC arm microkernel (C) 1998-2013 TU Dresden Rev: rexported compiled with gcc 4.8.3 for i.MX6 [] Build: #3 Wed Mar 11 16:43:41 CET 2015 Calibrating timer loop... done. MDB: use page size: 20 MDB: use page size: 12 SIGMA0: Hello! KIP @ 10002000 allocated 4KB for maintenance structures SIGMA0: Dump of all resource maps RAM:------------------------ [4:10000000;10000fff] [0:10063000;1008ffff] [0:10097000;10097fff] [0:1009f000;1013ffff] [4:10140000;10171fff] [0:10172000;10177fff] [4:10178000;10193fff] [0:10194000;110fffff] [4:11100000;11133fff] [0:11134000;4effffff] IOMEM:---------------------- [0:0;fffffff] [0:50000000;ffffffff] MOE: Hello world MOE: found 1031220 KByte free memory MOE: found RAM from 10000000 to 4f000000 MOE: allocated 1008 KByte for the page array @0x10194000 MOE: virtual user address space [0-bfffffff] MOE: rom name space cap -> [C:501000] BOOTFS: [11100000-11119474] [C:503000] l4re BOOTFS: [1111a000-11133598] [C:504000] vm-tz MOE: cmdline: moe --init=rom/vm-tz MOE: Starting: rom/vm-tz MOE: loading 'rom/vm-tz' Vmm started terminate called after throwing an instance of 'N2L413Runtime_errorE' MOE: task 270000679 exited with 127 The code stops at the beginning when it tries to create a VM : L4Re::chksys(env->factory()->create_vm(vm)); After reading through the code, I saw that the code example is expecting a linux-image and an initrd to be provided. Is it possible to tell me where these should be added in the build directory? In my test case, the linux-image will be replaced by a simple kernel image. Could someone help me to correct my test case. Many thanks in advance. Best regards, Mahdi

2 19

context::regs
by watermirror 03 May '15

03 May '15

hi,the implemention of Context::regs() is like this: return reinterpret_cast<Entry_frame*>(Cpu::stack_align(reinterpret_cast<Mword>(this + Size)) -1; how this algorithm came out?i think the memory of the object is allocated by c++ compiler, but why '(this + Size)' could get Entry_frame of a thread?

2 1

the syscall stack frame and Context::regs method
by watermirror 28 Apr '15

28 Apr '15

hi, i am reading the code about system call. after the sys_ipc_wrapper (in file kern/syscalls.cpp) is called.it get the thread's pointer by current_thread and then get the Syscall_frame. the code is like this: ... Thread *curr=current_thread(); Syscall_frame *f = curr->regs(); ... i can not understand the relationship between curr->regs() and the system call's stack frame.

2 1

about sysenter
by watermirror 28 Apr '15

28 Apr '15

hi ,in the file :l4re/pkg/l4sys/include/ARCH-x86/ipc-invoke.h, the comments says: We use ecx to store the user-level espand save eip onto the stack. but where could if find the corresponding code?

2 1

the first instruction in entry_sys_fast_ipc_c
by watermirror 28 Apr '15

28 Apr '15

hi, after entered the entry_sys_fast_ipc_c through sysenter, why the first instruction is 'pop %esp'?

2 1

How to solve the problem about multiple definition of clk_enable?
by Youren Shen 28 Apr '15

28 Apr '15

Hi, L4 hackers, To solve the problem about "undefined reference to `clk_get_rate'", I select COMMON_CLK in config L4_PLATFORM_GENERIC. But when I build the L4Linux this occurs: multiple definition of `clk_enable' l4linux/arch/l4/kernel/arch-arm/l4.c:63: first defined here So, Should I disable L4_CLK_NOOP in L4_PLATFORM_GENERIC? Thank you very much! Best Regards! Youren Shen

2 1