l4-hackers April 2015

l4-hackers@os.inf.tu-dresden.de

19 participants
33 discussions

Re: Using a second UART to control a serial device
by Reinier Millo Sánchez 18 Apr '15

18 Apr '15

Hi Clemens I have been testing something similar in other board (YSE5250-Exynos5). First you must guarantee that the UART device driver is compatible with the hardware or you must write an specific device driver. I have tried to make a GPS device driver using the S3C2410 UART based on the serial-drv package. To connect the uart on the user land with my server i have configured the HW.Device in a vbus with the IO server using this configuration: -- File: yse5250.devs local Hw = Io.Hw local Res = Io.Res Io.hw_add_devices { UART3 = Hw.Device { hid = "UART3"; Res.irq(86); Res.mmio(0x12C30000, 0x12C3ffff); } } To create the vbus, i have created the file yse5250.io: -- File: yse5250.io Io.add_vbusses { -- Create a virtual bus for a client and give access to UART3 uart03 = Io.Vi.System_bus(function () dev = wrap(Io.system_bus():match("UART3")); end); } To run my server using the UART3 on the vbus have used this configuration -- gps-drv.cfg -- Run GPS Driver for YSE5250 (Exynos 5250) require("L4"); -- Shortcuts local ld = L4.default_loader; local vbus_uart03 = ld:new_channel(); local platform_ctl = ld:new_channel(); local gps_srv = ld:new_channel(); -- Start the IO Server ld:start( { caps = { sigma0 = L4.cast(L4.Proto.Factory, L4.Env.sigma0):create(L4.Proto.Sigma0); icu = L4.Env.icu; platform_ctl = platform_ctl:svr(); uart03 = vbus_uart03:svr(); }, log = { "IO Server", "green" }, l4re_dbg = L4.Dbg.Warn, }, "rom/io rom/yse5250.devs rom/yse5250.io"); -- Start the GPS Driver Server conected to UART3 ld:start( { caps = { gps_srv = gps_srv:svr(); vbus = vbus_uart03; }, log = {"GPS Driver","blue"} }, "rom/gps_drv"); The server code is very similar to: /pkg/serial-drv/server/src/main.cc But in my case i have adjusted the UART to use the S3C2410 uart. Best regards On 04/18/2015 06:00 AM, l4-hackers-request(a)os.inf.tu-dresden.de wrote: > Message: 1 > Date: Fri, 17 Apr 2015 12:03:46 +0200 > From: "Pflaum, Clemens"<clemens.pflaum(a)mytum.de> > To:l4-hackers@os.inf.tu-dresden.de > Subject: Using a second UART to control a serial device > Message-ID:<4a79357eec3b3359e8b09e16a3fe0994(a)roundcube.lrz.de> > Content-Type: text/plain; charset=US-ASCII; format=flowed > > Hi L4 Hackers, > Im currently running Fiasco.OC with L4Re on my BananaPi. I'm trying to > control a serial device (Pololu Servo Controller) by sending a small > series of Bytes over a second UART ( not UART 0 since im getting the > console from there ). Via documentation I've found out that UART 3 is at > 0x01C28C00 and is a U6_16550A, so I'm hoping the driver in > /pkg/drivers-frst/uart/src/uart_pxa.cc will be compatible with that. > Where and how would I have to go about initiating my UART 3? By writing > a new platform for BPi in /pkg/bootstrap/server/src/platform? The > function set_stdio_uart(&_uart); made me think its only the "console" > UART. Or do I have to instantiate some kind of Hw.Device like the gpio > in /pkg/io/config/arm-omap3.devs and put it on a new vBus like in > /pkg/io/doc/example.io ? > > Or am I thinking way too complicated and it is as simple as editing the > /pkg/serial-drv/server/src/main.cc : > > bool > Serial_drv::init() > { > int irq_num = 37; > // How can i find out what this number refers to/do i have to > change it at all? > l4_addr_t phys_base = 0x1000a000; > // change to 0x01C28C00 > #if 0 > int irq_num = 74; > l4_addr_t phys_base = 0x49020000; > #endif > l4_addr_t virt_base = 0; > > if (l4io_request_iomem(phys_base, 0x1000, L4IO_MEM_NONCACHED, > &virt_base)) > { > printf("serial-drv: request io-memory from l4io failed.\n"); > return false; > } > printf("serial-drv: virtual base at:%lx\n", virt_base); > > L4::Io_register_block_mmio *regs = new > L4::Io_register_block_mmio(virt_base); > _uart = new (malloc(sizeof(L4::Uart_pl011))) L4::Uart_pl011(24019200); > //change to L4::Uart_pxa(what does this number mean?) > _uart->startup(regs); > > > Thanks for any answers in advance. > > Regards, > Clemensc...(a)mytum.de -- Lic. Reinier Millo Sánchez Centro de Estudios de Informática Universidad Central "Marta Abreu" de Las Villas Carretera a Camajuaní Km 5 1/2 Santa Clara, Villa Clara, Cuba CP 54830 "antes de discutir ... respira; antes de hablar ... escucha; antes de escribir ... piensa; antes de herir ... siente; antes de rendirte ... intenta; antes de morir ... vive"

1 0

Using a second UART to control a serial device
by Pflaum, Clemens 17 Apr '15

17 Apr '15

Hi L4 Hackers, Im currently running Fiasco.OC with L4Re on my BananaPi. I'm trying to control a serial device (Pololu Servo Controller) by sending a small series of Bytes over a second UART ( not UART 0 since im getting the console from there ). Via documentation I've found out that UART 3 is at 0x01C28C00 and is a U6_16550A, so I'm hoping the driver in /pkg/drivers-frst/uart/src/uart_pxa.cc will be compatible with that. Where and how would I have to go about initiating my UART 3? By writing a new platform for BPi in /pkg/bootstrap/server/src/platform? The function set_stdio_uart(&_uart); made me think its only the "console" UART. Or do I have to instantiate some kind of Hw.Device like the gpio in /pkg/io/config/arm-omap3.devs and put it on a new vBus like in /pkg/io/doc/example.io ? Or am I thinking way too complicated and it is as simple as editing the /pkg/serial-drv/server/src/main.cc : bool Serial_drv::init() { int irq_num = 37; // How can i find out what this number refers to/do i have to change it at all? l4_addr_t phys_base = 0x1000a000; // change to 0x01C28C00 #if 0 int irq_num = 74; l4_addr_t phys_base = 0x49020000; #endif l4_addr_t virt_base = 0; if (l4io_request_iomem(phys_base, 0x1000, L4IO_MEM_NONCACHED, &virt_base)) { printf("serial-drv: request io-memory from l4io failed.\n"); return false; } printf("serial-drv: virtual base at:%lx\n", virt_base); L4::Io_register_block_mmio *regs = new L4::Io_register_block_mmio(virt_base); _uart = new (malloc(sizeof(L4::Uart_pl011))) L4::Uart_pl011(24019200); //change to L4::Uart_pxa(what does this number mean?) _uart->startup(regs); Thanks for any answers in advance. Regards, Clemens c...(a)mytum.de

1 0

the kernel's output
by 水镜 17 Apr '15

17 Apr '15

hi , there're a lot of printf in fiasco kernel, but i can not seen any output on the screen. how could i turn these things on?

2 1

the ldscripts of L4Re
by 水镜 16 Apr '15

16 Apr '15

hi, the L4Re has three ldscripts: main_dyn.ld main.rel.ld main.stat.ld what are the differences?

2 1

How to track execution process of fiasco user mode applications？
by zhou.li9＠zte.com.cn 16 Apr '15

16 Apr '15

I found that fiasco does not support GDB, in order to track execution process of fiasco user mode applications,what method can be used? -------------------------------------------------------- ZTE Information Security Notice: The information contained in this mail (and any attachment transmitted herewith) is privileged and confidential and is intended for the exclusive use of the addressee(s). If you are not an intended recipient, any disclosure, reproduction, distribution or other dissemination or use of the information contained is strictly prohibited. If you have received this mail in error, please delete it and notify us immediately.

2 1

mmu in bootstrap
by 水镜 16 Apr '15

16 Apr '15

hi, i want to know, whether the bootstrap in l4re(x86) will initialize the MMU, setup pagetable? i am trying to debug the fiasco with gdb and qemu. when i attach to the qemu before system startup, i can check memory like 0x1100000.after the system startup, the gdb tell me can not access memory if i check 0x1100000 again.

2 1

IPC stream magic
by teclis High Elf 11 Apr '15

11 Apr '15

I have a complex nested structure that looks something like this: typedef struct struct_A { int i; struct struct_B[5]; int j; } using an IPC stream I do: struct_A a; ios.put(a); and then in the server process I do: struct_A b; ios.get(b); ( ios is a L4::Ipc::Iostream ) and magically my complex nested structure reappears with all the data intact in the server process running in another address space. As the IPC Streams are not well documented would someone be able to explain to me how my complex nested structure got automatically marshalled in the client and unmarshalled in the server process?

2 1

Re: ARM with Qemu
by Nicolas VARONA 09 Apr '15

09 Apr '15

Hi, Thanks for your answer and your help. >Could also be the uart issue? But entering jdb always works for me. Even if I can't give inputs to the bare metal application on Qemu, I can also enter into the JDB. Is that mean that all interruptions are well handled? So the uart issue seems more probable. >Which kind of panic? I firstly tested my L4linux on Qemu for the Zinq board and the boot finishes well (with the problem of inputs that I told you before). Nonetheless, with the same image on the board, I have this message: [...] Freeing unused kernel memory: 116K (0230f000 - 0232c000) potentially unexpected fatal signal 11. CPU: 0 PID: 1 Comm: init Not tainted 3.16.0-l4 #152 task: 05c23ac0 ti: 05c26000 task.ti: 05c26000 PC is at 0x0 LR is at 0x0 pc : [<00000000>] lr : [<00000000>] psr: 60000010 sp : bf73cef0 ip : 00000000 fp : 00000000 r10: 00000000 r9 : 00000000 r8 : 00000000 r7 : 00000000 r6 : 00000000 r5 : 00000000 r4 : 00000000 r3 : 0000c50c r2 : 00000000 r1 : 00000000 r0 : 00000000 vcpu: b3000c00 vcpu-state: 00000001 Flags: nZCv IRQs on FIQs on Mode USER_32 ISA ARM Segment user CPU: 0 PID: 1 Comm: init Not tainted 3.16.0-l4 #152 [<0200c9c8>] (unwind_backtrace) from [<020055e8>] (show_stack+0x10/0x14) [<020055e8>] (show_stack) from [<0202844c>] (get_signal_to_deliver+0x204/0x490) [<0202844c>] (get_signal_to_deliver) from [<02006be8>] (do_signal+0x114/0x448) [<02006be8>] (do_signal) from [<0200a210>] (l4x_vcpu_entry_c+0xa94/0x1da8) [<0200a210>] (l4x_vcpu_entry_c) from [<00000000>] ( (null)) Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b CPU: 0 PID: 1 Comm: init Not tainted 3.16.0-l4 #152 [<0200c9c8>] (unwind_backtrace) from [<020055e8>] (show_stack+0x10/0x14) [<020055e8>] (show_stack) from [<022441a4>] (panic+0x7c/0x1e0) [<022441a4>] (panic) from [<0201e6a8>] (do_exit+0x708/0x7a0) [<0201e6a8>] (do_exit) from [<0201e80c>] (do_group_exit+0x3c/0x9c) [<0201e80c>] (do_group_exit) from [<02028390>] (get_signal_to_deliver+0x148/0x490) [<02028390>] (get_signal_to_deliver) from [<02006be8>] (do_signal+0x114/0x448) [<02006be8>] (do_signal) from [<0200a210>] (l4x_vcpu_entry_c+0xa94/0x1da8) [<0200a210>] (l4x_vcpu_entry_c) from [<00000000>] ( (null)) ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b panic: going to sleep forever, bye l4linux | panic: going to sleep forever, bye Thanks in advance for your help, Nicolas >Hi, > >On Mon Mar 02, 2015 at 15:10:04 +0100, Nicolas VARONA wrote: >> I am trying to set up a simulator with Qemu and l4linux ARM to >> simulate the Zynq board. I have successfully compiled Fiasco and L4 >> with the tool chain "arm-linux-gnueabi-gcc". I succeeded to launch >> l4linux but I have no input on l4linux when it's running on Qemu. >> Nevertheless, the fiasco jdb can be invoked. After reading the mailing >> list I changed the hello world program to take inputs and tried a bare >> metal application with l4re with the same result (I didn't modify the >module list). >> >> So, I tried to do the same thing with the board and I have inputs with >> the l4 bare metal application > >So I looked a bit at this and it seems to me that there's something strange >with uart rx in Qemu, or at least which only shows up in Qemu. >I need to investigate that further. > >> and a kernel panic for the l4linux. > >Which kind of panic? > >> I boot >> with the uboot image on it. Nonetheless, using uImage for qemu doesn't >> change anything: >> >> ./qemu-system-arm -M arm-generic-fdt-plnx -m 512M -kernel >> /path/bootstrap.uimage -dtb /path/devicetree.dtb -serial mon:stdio >> >> I tried to compile the u-boot from Xilinx and Qemu freezes when I >> launch the l4 application. > >Could also be the uart issue? But entering jdb always works for me. > >> To be sure I have done things right, I also tried the modified hello >> world program on x86 intel and it works well. Then I launched a >> Petalinux with Qemu and a uImage with uboot and it works. >> >> My Qemu is from Xilinx: QEMU emulator version 2.0.50 > >Oh, good to know. I tried the normal one.

2 12

Question about L4/Fiasco running the kernel with interrupts disable
by deng.chao1＠zte.com.cn 09 Apr '15

09 Apr '15

Hi all， I have read the wikipedia website of L4 kernel(http://en.wikipedia.org/wiki/L4_microkernel_family), it says that L4/Fiasco was designed "fully preemptible to achieve a low interrupt latency " at first, however "the complexities of a fully preemptible design resulted in later versions of Fiasco to return to the traditional L4 approach of running the kernel with interrupts disabled ". I am very interested in the kernel's interrupt latency. I have check the latest versions of Fiasco kernel in running, and it keeps interrupts disabled indeed. So I wonder whether there was any early version of L4/Fiasco which supported fully preemptible? Or was there any article talked about this ? Thanks！

2 1

Question about L4/Fiasco running the kernel with interrupts disable
by cui.yunfeng＠zte.com.cn 08 Apr '15

08 Apr '15

1 0

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

2001

2000

1999

1998

l4-hackers April 2015