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(no subject)
by zhou.li9＠zte.com.cn 31 Mar '15

31 Mar '15

Now I want to debug Fiasco.OC kernel with JDB, the version of Fiasco.OC is 2014092821. Mentioned in a jdb.pdf document section 4.14, need to use RMGR to load the symbol table, but I did not find any manpage on the RMGR. where is the manpage or how to load the symbol table? -------------------------------------------------------- ZTE Information Security Notice: The information contained in this mail (and any attachment transmitted herewith) is privileged and confidential and is intended for the exclusive use of the addressee(s). If you are not an intended recipient, any disclosure, reproduction, distribution or other dissemination or use of the information contained is strictly prohibited. If you have received this mail in error, please delete it and notify us immediately.

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L4 and Lua interaction
by daniel krefft 30 Mar '15

30 Mar '15

Hi there, please can you give us a short overview about the L4 and Lua interaction/integration? The most important aspect is to understand how Lua-Scripts are used to create/manage the VBus. In particular from which module/component are the Lua-Scripts read/processed (NED, SIGMA0)? We found an example about Ankh (ankh.vbus, aw.lua, lwip.lua). Maybe it is possible to exemplify it via Ankh. Regards, Daniel -- Mit freundlichen Grüßen Daniel Krefft ***************************************************************** * Daniel Krefft M.Sc. * * T: +49-89-289-18791 * * * Technische Universitaet Muenchen * Fakultaet fuer Informatik - F13 (Prof. Baumgarten) * Boltzmannstr. 3 * D-85748 Garching bei Muenchen * Germany *****************************************************************

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microkernel as an instance in oracle virtual box
by Gayathri Nagarajan 24 Mar '15

24 Mar '15

Is it possible to run the microkernel Fiasco.oc directly as an instance in Oracle virtual box (just like other operating systems like Ubuntu, windows etc that are executed) ? If so, how do I do it?

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Support for Raspberry Pi 2 B and/or Odroid C1
by daniel krefft 24 Mar '15

24 Mar '15

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi there, we're are interested in running Fiasco.OC on the Raspberry Pi 2 (Broadcom BCM2836 ARM Cortex-A7) or Odroid C1 (Amlogic S805 Cortex A5). Is there any support for the boards yet? Best regards, Daniel - -- Mit freundlichen Grüßen Daniel Krefft ***************************************************************** * Daniel Krefft M.Sc. * * T: +49-89-289-18791 * * * Technische Universitaet Muenchen * Fakultaet fuer Informatik - F13 (Prof. Baumgarten) * Boltzmannstr. 3 * D-85748 Garching bei Muenchen * Germany ***************************************************************** -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAEBAgAGBQJVD+5AAAoJEJwTN+De5ZtpDfgH/1x7WIHYutLEWJmP23lhSnAm jp1NLmUL1kaFPGrsTr0Q4WfBtn6iVTFYbmoDXoMZxmen4Ne0SomuftSAHePkBwOm SH6udmQir5b6C0hWJSGdQ0CkY+YemcR3LvM3poNzpJtNAJvTiCRNE6qeI4WZn5TY ocNb3AzzNZ4ruZ6QBdtiwfkpAAABZQSiWM6xtcHIVckGezWuW+qC3ZLfvNK08U/i 4Up0eHIc2dldgrGCvzotC0j6LW7urinVG0e6rBFImrup1wLnTlJAJwua0wzf5uGT omkS1dE4u5RQ7BkYHWfwaAApI0Cm5vNVu90ObfVsBKSLPE1fluxmZ+SNLWEhgt0= =TBGn -----END PGP SIGNATURE-----

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the implemention of l4_ipc_send
by 水镜 24 Mar '15

24 Mar '15

hi, where could i find the implemention of l4_ipc_send?

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Help with RaspberryPI USB on Fiasco.OC+Genode
by Reinier Millo Sánchez 23 Mar '15

23 Mar '15

Hi GenodeOS and L4-Hackers community I'm trying to use DWC_OTG USB Driver for RaspberryPI, using Fiasco.OC as microkernel with Genode. I have tested the USB driver using Genode bare metal hardware on RaspberryPI and works fine. I have reviewed the post published by Simon Arlott about the FIQ and Bell IRQ: http://permalink.gmane.org/gmane.linux.kernel.rpi/438 Also I have reviewed the correction implemented by Norman Feske in the IRQ controller for Genode bare metal hardware: repos/base-hw/src/core/include/spec/rpi/pic.h To use Fiasco.OC as microkernel in Genode I have adapted the patch published in: http://sourceforge.net/p/genode/mailman/message/33071769/ Based on it, i have tried to use the same idea of Norman Feske, modifying the Fiasco.OC's IRQ's controller as shown below: ------ kernel/fiasco/src/kern/arm/bsp/bcm2835/mem_layout-arm-bcm2835.cpp ------ index aab5906..4385ebe 100644 @@ -8,5 +8,6 @@ public: Pic_phys_base = 0x2000b200, Watchdog_phys_base = 0x20100000, Uart_phys_base = 0x20201000, + Usb_dwc_otg_base = 0x20980000, }; }; ---------- kernel/fiasco/src/kern/arm/bsp/bcm2835/pic-arm-bcm2835.cpp ---------- index 20ed280..13fa623 100644 @@ -7,6 +7,83 @@ IMPLEMENTATION [arm && bcm2835]: #include "irq_mgr.h" #include "mmio_register_block.h" #include "kmem.h" +#include "warn.h" + +class Usb_dwc_otg : Mmio_register_block{ +private: + enum{ + Core_irq_status_reg = 0x14, + Guid_reg = 0x3c, + Host_frame_number_reg = 0x408, + }; + bool is_sof() const { return read<Mword>(Core_irq_status_reg)&0x8; } +}; + +PUBLIC +Usb_dwc_otg::Usb_dwc_otg() +: Mmio_register_block(Kmem::mmio_remap(Mem_layout::Usb_dwc_otg_base)) +{ + + write<Mword>(read<Mword>(Guid_reg)&0x3FFFC000, Guid_reg); +} + +PRIVATE +static bool +Usb_dwc_otg::need_trigger_sof(Mword host_frame, Mword scheduled_frame) +{ + Mword const max_frame = 0x3fff; + + if (host_frame < scheduled_frame) { + if (scheduled_frame - host_frame < max_frame / 2) + return false; /* scheduled frame not reached yet */ + else + return true; /* scheduled frame passed, host frame wrapped */ + } else { + if (host_frame - scheduled_frame < max_frame / 2) + return true; /* scheduled frame passed */ + else + return false; /* scheduled frame wrapped, not reached */ + } +} + +PUBLIC +bool +Usb_dwc_otg::handle_sof() +{ + if (!is_sof()) + return false; + + static Mword cnt, stat_cnt, filter_cnt, kick_cnt, trigger_cnt; + + stat_cnt++; + if (stat_cnt == 8000) { + WARN("kicked: %d filtered: %d triggered: %d", kick_cnt, filter_cnt, trigger_cnt); + stat_cnt = 0; + } + + cnt++; + if (cnt == 8*20) { + cnt = 0; + return false; + } + + if (read<Mword>(Guid_reg)&0x40000000) + kick_cnt++; + + if ((!read<Mword>(Guid_reg)&0x80000000) || (read<Mword>(Guid_reg)&0x40000000)) + return false; + + if (Usb_dwc_otg::need_trigger_sof(read<Mword>(Host_frame_number_reg)&0x3fff, read<Mword>(Guid_reg)&0x3fff)) { + trigger_cnt++; + return false; + } + + filter_cnt++; + + write<Mword>(read<Mword>(Core_irq_status_reg)|0x8, Core_irq_status_reg); + + return true; +} class Irq_chip_bcm : public Irq_chip_gen, Mmio_register_block { @@ -29,6 +106,9 @@ public: bool is_edge_triggered(Mword) const { return false; } void set_cpu(Mword, Cpu_number) {} void ack(Mword) { /* ack is empty */ } + +private: + Usb_dwc_otg _usb; }; PUBLIC @@ -97,6 +177,11 @@ Irq_chip_bcm::irq_handler() { b = 0; p = read<Mword>(Irq_pending_1); + if(p==8){ + if(_usb.handle_sof()){ + return; + } + } } else if (p & 0x200) { I have tried to test the *usb_hid *example on Genode using Fiasco.OC as microkernel make run/usb_hid The example compiles fine. When I test it in the emulator QEMU get the following output KERNEL: Warning: kicked: 0 filtered: 0 triggered: 7950 KERNEL: Warning: kicked: 0 filtered: 0 triggered: 15900 KERNEL: Warning: kicked: 0 filtered: 0 triggered: 23850 KERNEL: Warning: kicked: 0 filtered: 0 triggered: 31800 When have tested it on real hardware never get the kernel warning. It seems that the *Kick* and *Num_valid* bits are not modified by the USB driver. After that, I have tried to log the USB driver IRQ, setting #define DEBUG_IRQ 1 in the file repos/dde_linux/src/lib/usb/include/lx_emul.h Setting this value, the USB driver will log every IRQ handled by the function *_handle()* and *_handle_one()***in the USB driver. In the Genode bare metal hardware it works fine, but when tried it with Fiasco.OC, the IRQ handler *_handle()* and *_handle_one()* are never logged. There's something wrong in my implementation? Someone has tested the USB driver using Fiasco.OC and Genode together? Why Fiasco.OC's IRQ's controller is not calling the IRQ's handler defined in the USB driver? I'm using Genode commit 63293950261bfb17497433c36a3d62e6e1d813b3, Fiasco.OC r56 and DWC_OTG commit d08b205cfe01925667f3591117b6d3e1087b4e19. Best regards -- Lic. Reinier Millo Sánchez Centro de Estudios de Informática Universidad Central "Marta Abreu" de Las Villas "antes de discutir ... respira; antes de hablar ... escucha; antes de escribir ... piensa; antes de herir ... siente; antes de rendirte ... intenta; antes de morir ... vive"

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Help to measure the Fiasco.OC's real-time capabilities
by Reinier Millo Sánchez 23 Mar '15

23 Mar '15

Hi L4 Hackers community I want to use Fiasco.OC to construct real-time's systems. I want to do some benchmarks over Fiasco.OC, to measure the performance in different hardware platforms and compare the results with tests made to others solutions based maybe on Linux Kernel. For now i want to test the real-time capabilities on some platforms, measuring some aspects of Fiasco.OC (in time or cycles): - Execution mode switch (user-kernel) - Thread/Context switch on the CPU - Scheduler algorithm - IPC Mechanism - Thread/Task creation/destruction Somebody have measured this elements in Fiasco.OC or can give me some ideas? Best regards -- Lic. Reinier Millo Sánchez Centro de Estudios de Informática Universidad Central "Marta Abreu" de Las Villas "antes de discutir ... respira; antes de hablar ... escucha; antes de escribir ... piensa; antes de herir ... siente; antes de rendirte ... intenta; antes de morir ... vive"

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Moe::Boot_fs::init_stage1()
by 水镜 22 Mar '15

22 Mar '15

Hi, i am reading the source of the moe. there's a line: Moe::Boot_fs::init_stage1();‍ what it is for? when i comment it. the hello example can still run correctly.‍

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the editor for Fiasco.OC
by cui.yunfeng＠zte.com.cn 19 Mar '15

19 Mar '15

I am reading Fiasco.OC source code, but didn't find a suitable editor. As the following code, the eclipse or Source Insight can't identify the class hierarchy. I want to know which editor is used by Fiasco.OC developer, Thanks ! class Kernel_uart { public: }; .... EXTENSION class Kernel_uart : public Uart { private: };

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L4Re Hello World Qemu vs Hardware
by André Bispo 17 Mar '15

17 Mar '15

Hello guys,I was trying to run Fiasco and L4 and i successfully created the ISO image and ran it on QEMU.How can i run it on my pc hardware? Can you guys provide me some steps on how to do it? Thank you in advance,André Bispo.

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