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Question about schedule policy
by Kevin 04 Nov '14

04 Nov '14

Hello, I know the class "Task" in fiasco is equaled with the word "Domain" in VMM, but I can't find some schedule policy about Task in fiasco, all I find is scheduling about Thread in class Context and sched_context. So, is there any schedule policy about Task? thanks, kevin

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is there a way to run the compiled arm on Nexus S ?
by cem akpolat 04 Nov '14

04 Nov '14

Dear all, I have compiled couple of days ago l4android for arm architecture, and now I want to boot it on Nexus S, however, I couldn't find a way to tun bootstrapLinuxAndroid.elf file on arm based architecture. I have already seen in some research papers (one of them is as follows). http://www.isti.tu-berlin.de/fileadmin/fg214/liebergeld/spsm03-lange.pdf How could be l4android booted on the Nexus S? Thanks, Best Regards, Cem Akpolat

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FOSDEM 2015 - CfP: Microkernels DevRoom
by Vasily A. Sartakov 01 Nov '14

01 Nov '14

Greetings. ---- FOSDEM 2015 - CfP: Microkernels DevRoom I would love to announce the Call for Participation in the FOSDEM'15 Microkernel DevRoom. FOSDEM’15 will be held at the ULB Campus Solbosch on Saturday 31 January and Sunday 1 February 2015 and Microkernel devroom is scheduled on Sunday (01 February). Topics accepted include, but are not limited to: * Kernels, environments and frameworks * Hardware support: architectures, drivers * Languages and tools * Use cases, experiences, lessons learned and demos * Technical challenges and issues * Testing and support * Community building. Please use Pentabarf [1] system to submit your proposals. You do not need to create new account if you already have one. If the password is lost you can recovery it. Moreover, we have the devroom mailing list [2] Within submission please provide: * Title of your talk * Abstract, one or two paragraphs * Information about speaker: Name, bio, photo * Length of the talk. Each talk is limited to 45 minutes but can be less. Important dates: * Nov 28: Deadline for submissions * Dec 01: Speakers notified of acceptance * Dec 08: Schedule published Please do not hesitate to forward this CfP to anyone interested in participating. 1. https://penta.fosdem.org/submission/FOSDEM15 2. https://lists.fosdem.org/listinfo/microkernel-devroom ---- -- Vasily A. Sartakov sartakov(a)ksyslabs.org

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Dummy irq
by teclis High Elf 01 Nov '14

01 Nov '14

If I wanted to create a dummy irq that didn't actually exist in hardware but I could use for asynchronous notification between processes or between a hypervisor and a VM how would I do that in L4Re? What would the dummy entry look like in the .devs file? thanks

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Microkernel Stammtisch Dresden: Nov 6, Shamrock
by Julian Stecklina 29 Oct '14

29 Oct '14

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello fellow microkernel hackers, for everyone outside the Dresden, Germany area this mail is unfortunately off-topic. For everyone else there is going to be another Microkernel Stammtisch on Thursday, November 6th in the Shamrock Irish Pub[1]. If you intend to join, please leave a note using the link below, so I can reserve a table: https://dudle.inf.tu-dresden.de/ukvly-beer/ See you there, Julian [1] Kleine Brüdergasse 1, Dresden -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEARECAAYFAlRQL34ACgkQ2EtjUdW3H9l5qwCdHVLdLwthN4i5n8p7pQrqmr46 JzgAn18ML6+KoyLQZGEwg3jQW9CzOmUv =wapd -----END PGP SIGNATURE-----

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memcpy(): alignment error
by ba_f 25 Oct '14

25 Oct '14

Hello L4-Hackers, i get an "alignment error" when trying to memcpy(). The error occurs in a raw L4-Task (how do u "officially" name that?), no L4Linux. However, the error comes with the following line: memcpy(0x80006e80, 0x80006e84, 4); And this is the message: KERNEL0: alignment error at 80006ece (PC: 00079be8, SP: 80006b08, FSR: 410801, PSR: 60000010) No signal handler found Any idea? Thanks, again. PS: I don't know if the Fiasco Debugger would help for this problem, but i didn't have time to learn working with it, yet. Sorry for that.

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exec()
by teclis High Elf 23 Oct '14

23 Oct '14

Could some one please point me to or give me example code to do the L4Re equivalent of UNIX exec(), spawn a new process? thanks

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dynamic loading
by teclis High Elf 21 Oct '14

21 Oct '14

Does L4Re support dynamic loading? Is there an elf loader or shell? If so how do I do it? I want to run directly with L4Re. No l4linux. thanks

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SMP for L4Linux on i.MX6
by Uwe Geuder 19 Oct '14

19 Oct '14

Hi! We have an i.MX6 quadcore SoC and obviously we would like to use more than 1 core in L4Linux. So far I have not succeeded to do that. jdb shows 4 CPUs and some tasks on different ones, so I assume our Fiasco configuration supports SMP. Still all L4Linux tasks are on the same one and CPU stress testing shows clearly that only 1 CPU is in use. >From an earlier posting on this list I found the L4.Proto.Scheduler configuration for ned. I tried various options but there was no effect, L4Linux user space runs on 1 core only. -- CPUs 1 + 2 -- scheduler = L4.Env.user_factory:create(L4.Proto.Scheduler, 0x18, 0x8, 6), -- maybe no mask means all CPUs? scheduler = L4.Env.user_factory:create(L4.Proto.Scheduler, 0x18, 0x8), Next I looked at our L4Linux configuration and indeed CONFIG_SMP was not set. However after enabling it the kernel does no longer build: arch/arm/mach-imx/built-in.o: In function `imx_smp_prepare': /home/geuder/projects/c4c/l4-bundle/l4linux/arch/arm/mach-imx/platsmp.c:79: undefined reference to `scu_enable' /home/geuder/projects/c4c/l4-bundle/l4linux/arch/arm/mach-imx/platsmp.c:79: undefined reference to `scu_enable' arch/arm/mach-imx/built-in.o: In function `imx_smp_init_cpus': /home/geuder/projects/c4c/l4-bundle/l4linux/arch/arm/mach-imx/platsmp.c:71: undefined reference to `scu_get_core_count' arch/arm/mach-imx/built-in.o: In function `v7_secondary_startup': /home/geuder/projects/c4c/l4-bundle/l4linux/arch/arm/mach-imx/headsmp.S:33: undefined reference to `v7_invalidate_l1' /home/geuder/projects/c4c/l4-bundle/l4linux/arch/arm/mach-imx/headsmp.S:35: undefined reference to `secondary_startup' The SCU http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0407e/CDDEHD… has to do with cache coherency, obviously important on SMP. The SCU code is in native ARM, but not in L4 ARM. I somehow have the feeling just copying it is not enough. Does the virtual CPU seen by L4Linux need to control/use the SCU or is that something made completely transparent by the virtual cpu offered by L4? v7_secondary_startup code is behind !defined(CONFIG_L4). The code does a lot of MMU initializion stuff, so my guess is this cannot worked unchanged under L4. So the question is: Is SMP for i.MX6 unimplemented or at least untested or am I doing something completely wrong here? Somebody here mentioned VCPU. I have not studied that concept yet. We have CONFIG_L4_VCPU=y Regards, Uwe Geuder Nomovok Ltd. Tampere, Finland uwe.gxuder(a)nomovok.com (bot test: humans correct 1 obvious spelling error)

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Teaching OS Course notes
by teclis High Elf 17 Oct '14

17 Oct '14

Hi, I understand that Fiasco/L4Re is used as the teaching operating system at TU Dresden. Are there any course notes or lab notes available for courses at TU Dresden that used and/or covered Fiasco/L4Re? All the lab tutorials and course notes pertaining to the teaching operating systems used at MIT and Stanford are available online but I couldn't find anything similar for Fiasco. thanks

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raw L4Task: Flash Access & Variable
by ba_f 16 Oct '14

16 Oct '14

Hello and thank u so far, >> Adam wrote: > It is possible. But of course there needs to be a driver for your flash > and a filesystem (if needed). And there's none. > There's a tmpfs, i.e. a filesystem that can store files, however, not > across reboots. Maybe that helps you already? Yes, volatile storage would do the trick. Unfortunately, i need some help here, too. :( I've found a post from Adam, concerning tmpfs: http://os.inf.tu-dresden.de/pipermail/l4-hackers/2014/006244.html I did all it says, and of course edited anything to my concerns. But my App fails to write at /tmp. fopen("/tmp/file", "wb") == NULL Maybe i do not place the fstab-file correct. Right now, fstab is located in the MODULE_SEARCH_PATH. But building the image does also work if there is no such file. Running the image, there are no complaints about a missing fstab. Is this correct behaviour? I also added fstab to my modules.list, without success. So... Is there another way to check if fstab is loaded correctly, besides using fopen(). -------- Here my files (shorted): # fstab / /tmp tmpfs defaults # modules.list entry app-cfg kernel fiasco -serial_esc roottask moe rom/app.cfg module l4re module ned module app.cfg module fstab [...] module libmount.so module libl4revfs-fs-tmpfs.so # app.cfg ld:start( "rom/app", { FSTAB_FILE = "rom/fstab" }); # Makefile REQUIRES_LIBS = libmount libl4revfs-fs-tmpfs

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[ASK] Basic L4Re
by Erry Pradana Darajati 13 Oct '14

13 Oct '14

Hello L4 Hackers I am working on a project with L4Re in Pandaboard for my College Final Project. And right now i am in a stuck. So far, i have already know how to boot, print and read from the serial port (UART3) of pandaboard. But i can't understand the fundamental / basic of L4Re itself. Like how to make a new program outside the main program of "hello" (i am using hello code all of this time to experimenting). And also how to access the memory of the host computer using L4Re code. Because the main goal of the project i am working on is be able to access the GPIO of Pandaboard. And also, is there is any way to recompile L4Re without recompiling all of the module it use. Because in my computer it took a time to recompile even the change is only a line of code Can anyone teach or show me how to make it ? Actually i already have read the documentation of L4Re, but i am still having a hard time understanding it. Thank you for any answer and feedback. -- *Regards,* *Erry Pradana Darajati | Student of Computer Engineering* *Politeknik Elektronika Negeri Surabaya / EEPIS, Indonesia*

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L4 Bootsrap Fiasco Addr
by Wölfel, Tobias 11 Oct '14

11 Oct '14

Hello All, I am working on porting Fiasco.OC to openrisc (or1k), but are stucked at booting the kernel. The problem is that the addr in boot_info.kernel_start is pointing to the beginning of the bootsrap, and therefore it will not start the kernel. In startup.cc there is the mbi, mb_info and mb_mod, which I suppose is the place where the addr is coming from. But where is it set exactly? For or1k IMAGE_MODE is used. The output of the bootstrapping is at the end. Thanks a lot for the help, Tobias " Loading fiasco [0x1103000-0x1104000] [0x1104000-0x11040ac] [0x11040ac-0x112c340] [0x112c340-0x1134468] [0x1135000-0x1135a84] [0x1135a84-0x1136000] boot_info.kernel_start 100 Loading sigma0 [0x100000-0x107ff4] [0x108000-0x10c17c] Loading foo find kernel info page... found kernel info page at 0x1103000 Regions of list 'regions' [ 100, 1d403] { 1d304} Boot bootstrap [ 128ac, 1291e] { 73} Boot mbi [ 17000, 171ab] { 1ac} Root Multiboot info [ 1d058, 1d0af] { 58} Boot mbi [ 100000, 10c17b] { c17c} Sigma0 sigma0 [ 1100000, 11001d3] { 1d4} Root Module [ 1103000, 1135fff] { 33000} Kern fiasco API Version: (87) experimental Sigma0 config ip:00100344 sp:0001b040 Roottask config ip:00000000 sp:00000000 Starting kernel fiasco at 00000100 "

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Thread synchronization with in the same address space
by teclis High Elf 10 Oct '14

10 Oct '14

I have two threads running in the same server. On thread handles incoming ipc messages from the clients in different address spaces and the other thread does the work. The thread handling the incoming ipc needs to pass an integer value to the worker thread. Could I synchronize them using int l4util_cmpxchg32 <https://os.inf.tu-dresden.de/L4Re/doc/group__l4util__atomic.html#gacb4a5e47…> (volatile l4_uint32_t <https://os.inf.tu-dresden.de/L4Re/doc/group__l4__basic__types.html#gac1d09f…> *dest, l4_uint32_t <https://os.inf.tu-dresden.de/L4Re/doc/group__l4__basic__types.html#gac1d09f…> cmp_val, l4_uint32_t <https://os.inf.tu-dresden.de/L4Re/doc/group__l4__basic__types.html#gac1d09f…> new_val) the worker thread could then check the value of dest to get the integer. Would the worker thread need to use an atomic read function when it reads the value of dest and if so which function would the worker thread use for the atomic read? thanks,

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examples/libs/l4re/c++/shared_ds/ds_clnt.cc
by teclis High Elf 10 Oct '14

10 Oct '14

>From examples/libs/l4re/c++/shared_ds/ds_clnt.cc line 49 : L4::Cap<L4::Irq> irq = L4Re::Util::cap_alloc.alloc<L4::Irq>(); It seems this template name L4::Cap and the function name L4Re::Util::cap_alloc are a bit misleading or only designate a sub-set of the objects functionality. In this line you are not just requesting permissions but getting a Unix style file handle that you then use to issue commands to the server on line 92: irq->trigger(); Is my understanding correct? At line 49 you are opening L4 equivalent of a Unix style file handle for sending commands to a server and not requesting permissions or am I over simplifying. thanks

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contiguous memory blocks and zero copy
by teclis High Elf 09 Oct '14

09 Oct '14

How does L4Re handle contiguous memory blocks? What are the system calls used to allocate and manage contiguous memory? Is it possible to do zero copy data transfer between drivers and if so how is it done in Fiasco (so in linux world you would say no copy_to_user() and copy_from_user() ) thanks,

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l4linux shutdown cleanup
by Masti Ramya Jayaram 09 Oct '14

09 Oct '14

Dear all, I would like to perform some cleanup operations after l4linux shuts down..such as zero out all the memory it used and re-encrypt the original vmlinux image. I would like to know how I could do this from sigma0 preferably or even in the fiasco kernel. Could anyone point me to where the clean up procedure (release of resources) occurs once l4linux shuts down? Thanks, Ramya

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JDB and thread ids
by teclis High Elf 09 Oct '14

09 Oct '14

What command in JDB gives me a list of thread IDs I can use with the other thread commands. I tried the list tasks and didn't see anything that looked like a thread id.

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Re: Graphical desktop, l4con, mag
by 000SKY 09 Oct '14

09 Oct '14

>>>> > > > fbdrv | To force a specific setting use a '-m <mode>' option. >>>> > > > fbdrv | L4Re[rm]: mapping for page fault failed with -34 @1a0000 >>>> > > > pc=1006452 >>>> > > > fbdrv | L4Re: unhandled exception: pc=0x1006452 There is a way to fix it. You can modify x86-legacy.devs,as follows: VGA = Hw.Device { hid = "PNP0900"; Res.io(0x3b0, 0x3bf); -- MDA Res.io(0x3c0, 0x3df); -- EGA/VGA Res.io(0x1ce, 0x1d0); -- Vbox Res.io(0x402, 0x402); -- QEMU Debug Port Res.mmio(0xa0000, 0xbffff); --Here lost a parameters. Changed to Res.mmio(0xa0000, 0xbffff,0xc000); },

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Ned,moe, l4linux interaction
by Masti Ramya Jayaram 01 Oct '14

01 Oct '14

Dear all, I see that in the default l4linux configuration, it uses ned, moe to start up. However, I am not sure about the run-time interaction between them. More specifically, a. Does l4linux need them during its run-time? For example, does l4linux go directly to sigma0 for memory or does it go through ned? b. Do ned and moe get killed once they start l4linux or not? Thanks, ramya

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Difference between capability and memory mapping
by Yuxin Ren 01 Oct '14

01 Oct '14

Hi All, I found in the kernel, the capability mapping and memory mapping have very similar code path. But I found their performance difference is around 1000 cycles. Is this true? If it is true, why do they have such large difference? If this gap does not make sense, it should be a bug in my test. Thank you very much. Best, Yuxin

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Repository Update
by Adam Lackorzynski 29 Sep '14

29 Sep '14

Hi, the repository and snapshots have been updated and I'm happy to announce a couple of new features: - L4Re supports ARM virtualization (HYP mode) now. There's a 'vmm' package that allows to run unmodified Linux, however, it might still have some rough edges. - With that ARM exception error codes have been changed to use HYP's HSR style, also for non-HYP kernels! - gcc-4.9 support, including libstdc++, and preparations for gcc-5 - EFI is available as a boot method now, both in 32 and 64 bit modes - x86 power management has been improved - Stackprotector support is available in L4Re now - The console server 'cons' has been added - Fiasco runs on more ARM targets, including Xilinx Zynq (Zedboard, Parallela), OMAP5, Allwinner (Cubieboard, Cubietruck) - More examples have been added - 3rd-party packages have been updated - L4Linux has been upgraded to version 3.16. Adam -- Adam adam(a)os.inf.tu-dresden.de Lackorzynski http://os.inf.tu-dresden.de/~adam/

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Question about the doc of L4Re
by lwf408498027 28 Sep '14

28 Sep '14

Hi hackers, I am learning the fiasco's source code recently, and I saw the doc in http://l4re.org/doc/ does not match with the code in l4re-snapshot-2014053111 such as: in class scheduler, there has some function: L4_msg_tag sys_run(L4_fpage::Rights, Syscall_frame *f, Utcb const *utcb); L4_msg_tag sys_idle_time(L4_fpage::Rights, Syscall_frame *f, Utcb *utcb); L4_msg_tag sys_info(L4_fpage::Rights, Syscall_frame *f, Utcb const *iutcb, Utcb *outcb); but in the document, the function are not the same: l4_msgtag_t info (l4_umword_t *cpu_max, l4_sched_cpu_set_t *cpus, l4_utcb_t *utcb=l4_utcb()) const throw () l4_msgtag_t run_thread (Cap< Thread > const &thread, l4_sched_param_t const &sp, l4_utcb_t *utcb=l4_utcb()) const throw () l4_msgtag_t idle_time (l4_sched_cpu_set_t const &cpus, l4_utcb_t *utcb=l4_utcb()) const throw () So, Is this doc out of date? and if the answer is yes, where can i find some fresh doc? if no, How to use the doc correctly? Thanks, Kevin

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L4_SYSCALL_INVOKE is a negative PC value？
by Zachary 28 Sep '14

28 Sep '14

hello everyone, In cache.h file(..\l4\pkg\l4sys\include\ARCH-arm\cache.h), a piece of code is as follows： l4_cache_op_arm_call(unsigned long op, unsigned long start, unsigned long end) { ... __asm__ __volatile__ ("@ l4_cache_op_arm_call(start) \n\t" "mov lr, pc \n\t" "mov pc, %[sc] \n\t" "@ l4_cache_op_arm_call(end) \n\t" : "=r" (_op), "=r" (_start), "=r" (_end) : [sc] "i" (L4_SYSCALL_MEM_OP), "0" (_op), "1" (_start), "2" (_end) : "cc", "memory", "lr" ); } My question is whether the code means that PC jumps to the address of L4_SYSCALL_MEM_OP(actual value is -0x00000010)? If it is true, then it means the address is 0xFFFFFFF0 ? My second question is whether the address 0xFFFFFFF0 corresponds to the sys_arm_mem_op in the following definition? (..\kernel\fiasco\src\kern\arm\asm_entry.h) /*********************************************************************/ /* The syscall table stuff */ /*********************************************************************/ .macro GEN_SYSCALL_TABLE .align 4 .global sys_call_table sys_call_table: .word sys_kdb_ke .word sys_kdb_ke .word sys_ipc_wrapper .word sys_arm_mem_op .word sys_invoke_debug_wrapper .word sys_kdb_ke .word sys_kdb_ke .word sys_kdb_ke .word sys_kdb_ke .word sys_kdb_ke .word sys_kdb_ke .endm Thank you so much. Best, Zachary

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What does idle thread do
by Yuxin Ren 27 Sep '14

27 Sep '14

Hi All, I want to know what kernel idle thread does. Does it just execute "halt" instruction or anything else? Where is code for the idle thread? Thank you so much. Best, Yuxin

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