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What is trampoline.S for?
by BVK Groups 17 Mar '06

17 Mar '06

Hi, Whenever i try to start executing first thread in a new address space, its pager is receiving pagefault (at 0x0000002b), eventhough none of the mapped code touches that place. Why is it? I found out that CHACMOS is mapping trampoline.S at that address. I What is this trampoline.S is for? I tried to understand trampoline.S code, but i couldn't. I didnt find any FAQ entry regarding this. Can anyone please help me here? NOTE: I am using pistachio-0.4 Thanks, -bvk

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Announce: OS Group of TU Dresden (TUD:OS) releases Live-Demo CD
by Norman Feske 13 Mar '06

13 Mar '06

The OS Group of Technische Universität Dresden (TUD:OS) has released a live demo CD of our operating system project. Some highlights of the Demo CD include a new approach for securing graphical user interfaces called Nitpicker, multiple L4Linux kernels running at the same time on top of a L4/Fiasco, a survey on our reuse of device drivers on the TUD:OS platform, native Qt-applications, the DOpE windowing system and a prototype of a secure E-commerce application based on TUD:OS. More information, an ISO image, and screenshots are available at the demo CD website: http://demo.tudos.org Norman Feske TU Dresden Operating Systems Group

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some weird performance result
by Sungkwan Heo 11 Mar '06

11 Mar '06

Hi all, I measured network I/O performance of native Linux-2.4 and Fiasco-1.2+L4Linux-2.4 using the netperf benchmark. The TCP streaming test results are following: Recv Socket Size bytes: Linux = 87380, L4Linux = 87380 Send Socket Size bytes: Linux = 16384, L4Linux = 16384 Send Message Size bytes: Linux = 16384, L4Linux=16384 Elapsed Time secs: Linux = 10.002, L4Linux = 10.002 Throughput MBytes/s: Linux = 11.22, L4Linux = 11.206 Utilization Send local % S: Linux = 11.359, L4Linux = 4.35 ... The last 2 lines indicates the network I/O throughput and CPU utilization for the network I/O. One weird thing is the L4Linux CPU utilization. It spent much less CPU cycles than the native Linux did. In my humble opinion, it is normal case because the L4 Fiasco schedules the L4Linux application (netperf) as a L4 process and L4Linux kernel doesn't have correct CPU usage information of the application. Is it correct?

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config for 2 L4Linux instances
by Sungkwan Heo 11 Mar '06

11 Mar '06

Hi all, Is there anyone who succeeded in running multiple L4Linux (2.4 or 2.6) instances on native fiasco, not fiasco-ux? If so, could I share the configuration and howto? Especially, I want to boot L4Linux-2.4 mounting root disk partition where RedHat 9.0 is already installed. I expect that another L4Linux-2.4 image can be loaded MODFS or TFTP. However I can't figure out how I can setup my L4 box to load any application that I want from where I want. Another issue is the second L4Linux need another root partition or not. Is it possible to the first L4Linux use hard disk partition and the second one use ramdrive? And as far as I know, the main purpose of fiasco-ux is just emulation and not real solution that has similiar architecture to WMware. right?

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Update on NICTA's secure embedded L4 project
by Kevin Elphinstone 10 Mar '06

10 Mar '06

Hi All, I'm please to announce the release of more information on the secure embedded L4 (seL4) project, including a reference manual of the experimental kernel API. You can get more info on the project's web page at http://www.ertos.nicta.com.au/research/sel4/ cheers - Kevin Dr. Kevin Elphinstone Senior Researcher and seL4 Project Leader National ICT Australia

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L4.Sec Implementation
by Anton Soppelsa 08 Mar '06

08 Mar '06

Hi, My name is Anton Soppelsa and I'm doing a PhD course at the "Istituto Gas Ionizzati" (Ionized Gas Institute) in Padova (Italy). I am a control system engineer and at the moment I'm involved in some work with a Motorola mv5500 Single Board Computer installed in a VME rack. As I am a free software supporter and I don't like too much our working developing platform as is based on the proprietary VxWorks operative system. For this reason I am interested in GPL-ed real time operative systems. I read the specification of the L4.Sec system, but unfortunately I am not able to fully understand the concept of capability space. Probably this happens because I am one of those that need to see how things are made to catch the concept of what they really are. Even if I don't think, at this moment, that L4.Sec is exactly what I need (because speed is my real priority), I'm anyway curious about how it works. So if your new project is at a point where you actually have some structures, or classes implementing the capability space, will your team be so kind to send me that piece of code? I will read it with interest in my spare time. Many thanks, Anton

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L4::Pistachio ARM GNU toolchain
by Shakthi Kannan 08 Mar '06

08 Mar '06

Greetings! I have downloaded pistachio-0.4.tar.bz2. I would like to know which GNU ARM toolchain needs to be used to cross-compile the above for ARM. Thanks, SK -- Shakthi Kannan, MS Software Engineer, Hexaware Technologies [E]: shakthimaan(a)yahoo.com [M]: (91) 98407-87007 [W]: http://www.shakthimaan.com [L]: Chennai, India __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com

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l4linux-2.6 build error
by Sungkwan Heo 07 Mar '06

07 Mar '06

Hi all, Though I had some hard time to run l4linux-2.6, I still get build error. When I build l4linux-2.6, the following error occured. As far as I know, a global variable (xtime) was defined twice. First, l4/pkg/generic_io/lib/clientlib/ARCH-x86/io_info.S Second, some header file included in l4linux-2.6/kernel/sysctl.c Any suggestion will help me much! $ cd l4linux-2.6 $ make menuconfig ... $ make ... CC arch/l4/l4lxlib/l4env/task.o CC arch/l4/l4lxlib/l4env/thread.o AR arch/l4/l4lxlib/l4env/lib.a GEN .version CHK include/linux/compile.h UPD include/linux/compile.h CC init/version.o LD init/built-in.o LD .tmp_vmlinux1 /home/drops/l4linux-2.6-env/l4/lib/x86_586/l4v2/libio.a(io_info.o)(.ros pace+0xc): In function `xtime': : multiple definition of `xtime' kernel/built-in.o(.bss+0x9650):/home/drops/l4linux-2.6-env/l4linux-2.6/ kernel/sysctl.c:1666: first defined here make: *** [.tmp_vmlinux1] Error 1 $

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make hello stops with an error
by Delitsyn Igor 03 Mar '06

03 Mar '06

Hi, I try to compile L4 kernel on x86 just to start with, but ¨make hello¨ results in an error in linking as follows: /usr/bin/ld: cannot find -lroot.o I was unable to locate this module manually. Any ideas? Thanks for taking a look at it. Best regards, Igor

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Re: PowerPC interrupt setup
by Kay-Uwe.Genz 02 Mar '06

02 Mar '06

Hi Joshua, hi @ all, I start this year with first experiments in implementation of an kernel (based on L4.X2) on PowerPC, mostly to learn more about PowerPC/HW and design philosophies. So I read your posting with attention and have some questions ... and hope your answers would made it easier for my to understand. You recommend "enabling virtual addressing immediatly". Did I understand it right, that you use virtual memory in kernel mode? Is this only for protection or means this, the kernel memory is vitual? There are other kernels using virtual memory in kernel mode? My design doesn't have a kernel section in the tasks address space (on 32 bit machines a task is 4GB). I agonise to solve some of the problems with this design. In the case StringItems used to send Msg's from one space to another (means copy the information in the kernel) the message buffer on both sides can scattered and located across page bounderies. Handling this seems easier if the kernel has the same view to memory and pionters to memory regions (buffers) but this destroy my approach of lockfreeness, because the String Buffers in different tasks can by overlap or locate at the same virtual adress. (The sendphase of StringItems should by interruptable and at any time it should by possible to handle as much as possible StrinItem sends in the same time.) Handling this in kernel with the view of real memory avoid overlapping buffer regions from different threads. Do you see the issue like I and is there a solution I didn't see? As I see on the homepage, the kernel runs on a G3 (aka PPC750). So you use the normal hardware table search? Thanks for helping. Regards Kay-Uwe. Am 07.02.2006 um 17:35 schrieb Joshua LeVasseur: > > The PowerPC jumps to predefined code locations when delivering > interrupts and traps, starting at 0x100 (with virtual addressing > disabled). You only need to install code at those locations; > PowerPC has no interrupt descriptors. I recommend enabling virtual > addressing immediately, even while handling page faults; I've seen > other kernels implement excessive logic in assembler, executing in > physical mode; that isn't necessary. I enable virtual addressing > within 19 or so instructions. > > Maybe try volume 3 here: > http://www-128.ibm.com/developerworks/eserver/articles/archguide.html > I've never read those documents; I used the 603 architecture manual > when porting L4Ka::Pistachio. > > Consider reading about how I made my L4Ka::Pistachio PowerPC > implementation frigging fast: > http://l4ka.org/projects/pistachio/powerpc/ppc.pdf > It covers: > - Fast system calls (without wasting a register for a system call > number, unlike all other kernels out there that I've seen) > - Fast address space ID management (the way ASIDs were meant to be > managed on the PowerPC, and again, the other kernels out there are > doing it wrong) > - Fast page hash management. Most kernels perform O(n) searches > through the page hash when manually locating an entry. I instead > perform O(1) lookups. > > I recommend that you avoid looking at open source kernels for > guidance. They don't push the limits of PowerPC. > > -Josh > > > > On Feb 7, 2006, at 16:18, Matthias Lange wrote: > >> Hi, >> >> I am stuck with porting the Fiasco microkernel to PowerPC. I can't >> find any clear documentation about how to setup a interrupt >> description table. So, these are my questions: >> >> 1. How is an interrupt descriptor formed on PowerPC? How does it >> look? >> 2. Where (in memory) do I need to store these descriptors? >> >> The IBM PowerPC Programming Manual gives me a good overview but no >> information on how to implement it. Can someone please point me to >> some meaningful documentation? >> >> Regards, >> >> Matthias. >> > > >

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