l4-hackers

l4-hackers@os.inf.tu-dresden.de

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2880 discussions

Share exist memory over IPC with L4Re
by Alexander Fratzer 16 May '17

16 May '17

Dear L4-Hackers, I have a very simple problem but I can't find the solution in the L4Re-Doc and examples so far. I wrote a very simple Unix-Like Shell with a Filesystem-Server and a Loader-Server and I implemented some Posix-Call as an abstraction for the communication with the Filesystem-Server (virtual). Now I have a problem of double copies for a read-Operation. I want a complete abstraction from the L4Re mechanisms and the underlying Client-Server architecture for the usage of this interface. The (bad) mechanism is as follow: Function (client side): ssize_t read(int fd, void *buf, size_t count) Algorithm: 1. Allocate Dataspace with size of count. 2. Send Cap of Dataspace to the Filesystem-Server. 3. Copy content of Dataspace to buf. 4. Cleanups. Function (server side): long VFSSrv::op_file_read(VFS::Rights, TaskRegistry::TaskId task, TaskRegistry::FileDescriptor fd, size_t size, L4::Ipc::Snd_fpage& flexp, size_t& rsize) Algorithm: 1. Get Dataspace-Cap from Ipc-fpage. 2. Reserve area with Region-Manager. 3. Attach Dataspace to the area. 4. Copy content of the file to the attached area. 5. Cleanups. This was my first working solution without focus on runtime but the creation of a new task from an ELF-File of 1.4 MB size takes 20 seconds on Cortex A8. This suxx so I have to optimize. Therefor I need a way to share the content of my file (virtual, heap allocated memory) without copying to the client but i don't find a way to share exist memory over IPC. I think I'm using the Dataspace-mechanism in a wrong way but maybe a Dataspace isn't the right choice in my case. A simple solution would be a new Filesystem which is based on Dataspaces but I don't want to do this. Have anybody a better idea? Thanks for help. Best regards Alex.

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Fiasco.OC: null-pointer dereference?
by Stefan Kalkowski 09 May '17

09 May '17

Dear L4-Hackers, recently, I started to upgrade the Fiasco.OC kernel version that is used by the Genode OS framework to the lastly released version (r72). I took the opportunity to upgrade, because the upcoming Genode release uses a fresh compiler toolchain that refused to build the very old Fiasco.OC kernel version that was used until now (r56). Everything went quite smoothly, and I'm glad to see how the kernel develops further. Thanks to all developers at this point! Unfortunately, I stumbled across an issue when it comes to thread destruction. In our system all threads are constructed and destructed by the roottask that is called 'core'. In some cases, not always but quite often, the Ram_quota pointer of the thread object is zero during the call of the Thread_oject's delete operator, which leads to a page-fault within the kernel-code. A simple check[1] before dereferencing the pointer solves the problem, but I wonder whether we will leak quota or memory then, or in general cover some more serious problem. Obviously, we have different usage patterns of syscalls, e.g.: the order of destructing IPC-gates, threads, IRQs, and tasks. Moreover, we still have some very few patches[2] so that the kernel meets our requirements. But none of them explains the thread's Ram_quota pointer getting zero. The page-fault triggers across all x86 and arm platforms that we use. Any hint would be very much appreciated, all the best! Stefan [1] https://github.com/skalk/foc/commit/2b01c9d16fd8e29e6af18fe750be2c8a312b4762 [2] https://github.com/skalk/foc/commits/r72 -- Stefan Kalkowski Genode Labs https://github.com/skalk · http://genode.org/

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Trying to build L4 on NixOS
by Mateusz Czaplinski 09 Apr '17

09 Apr '17

I'm trying to build L4 on NixOS in a VM (long term goal: try to learn how to replace NixOS's kernel with L4Linux, then maybe Genode). I'm getting an error like below: undefined reference to `__stack_chk_fail' during linking of bootstrap.elf - in a GCC's error-barf just after: [bootstrap] ==> Linking bootstrap.elf I've put up the precise Nix expression/script I'm using to build it on github - at: https://github.com/akavel/l4.nix/blob/0108dfcf8d84780e1ba884c41ece0d2dbf4dd… but what it generally boils down to is a sequence of commands like this: $ wget http://os.inf.tu-dresden.de/download/snapshots/l4re-core-2016082114.tar.xz $ tar xf l4re-core-2016082114.tar.xz $ cd l4re-core-2016082114 $ mkdir out $ cp src/l4/mk/defconfig/config.amd64 out/l4/.kconfig $ make -C src/l4 O=out/l4 olddefconfig $ make -C out/l4 I've tried various additional changes, based on some snippets found here and there on teh Internets, like: - adding V=0 to the last make (no idea what it does yet, just some cargo culting) - adding NIX_CFLAGS_COMPILE = "-fno-stack-protector"; to the Nix expression/script (also not really sure where it applies in the stack); but none of the above helped. Any idea what I could try doing to push it further? Thanks, /Mateusz.

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Questions about Fiasco.OC scheduler and L4Linux
by Marc CHALAND 02 Apr '17

02 Apr '17

Hi, I'm doing a study to port old software on top of Fiasco.OC. This soft uses routines which blocks thread scheduling between EnterRegion and LeaveRegion call. Is there any equivalent on TUDOS ? Did somebody already get this challenge ? I would like to know if L4Linux uses Fiasco.OC scheduler or a user land one ? For our i.MX7d board, Freescale provides Linux drivers on 4.1. I don't know yet how many drivers we will need. Do you think it is better to port drivers from 4.1 to L4Linux 4.3 or later or get a L4Linux 4.1. I have no idea about the complexity on doing this. Regards Marc

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L4linux __raw_writesl/readl undefined
by Manolis Ragkousis 01 Apr '17

01 Apr '17

Hello everyone, I am trying to enable sd card support on my zedboard running l4linux and I get this error: ERROR: "__raw_writesl" [drivers/mmc/host/mmci.ko] undefined! ERROR: "__raw_readsl" [drivers/mmc/host/mmci.ko] undefined! make[2]: *** [../scripts/Makefile.modpost:91: __modpost] Error 1 make[1]: *** [/home/manolis/repos/l4linux/Makefile:1173: modules] Error 2 make[1]: *** Waiting for unfinished jobs.... LD ldrImage GZIP vmlinuz LOCINST vmlinuz make[1]: Leaving directory '/home/manolis/repos/l4linux/build' make: *** [Makefile:150: sub-make] Error 2 In order to enable sd card support I understand that I need to enable MMC/SD/SDIO card support in the kernel + ARM AMBA Multimedia Card Interface support. I have followed the instructions from previous emails in this list [1][2]. What am I missing? Is there a config option which enables raw writes/reads on top of L4? Thank you for you time and help, Manolis [1] https://os.inf.tu-dresden.de/pipermail/l4-hackers/2014/006296.html [2] https://os.inf.tu-dresden.de/pipermail/l4-hackers/2014/006417.html

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Can't find device node in /dev/ directory!
by li94575 21 Mar '17

21 Mar '17

Hi, I added some drivers in l4linux, of course, I assigned the corresponding peripheral resources (iomem, irq) to these drivers. From the driver's output log, it seems that they all work well, but when entering the command line, I could not find any relevant device node in /dev/ directory. To my confusion, I can see these devices info in /sys/ directory. The command line args is showing below: mem=64M console=ttyLv0 l4x_rd=rom/ramdisk-" .. L4.Info.arch() .. ".rd ramdisk_size=4000 Any idea?

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Re: Extending l4sys by reading/writing register values of a preempted thread
by Christian Ludwig 21 Mar '17

21 Mar '17

Hi, > I want to implement a new syscall for getting/setting stored register > values of a specific thread (identified by its cap). Why not use ex_regs() on the thread to trigger an exception. That way, the attached userland exception handler can introspect the thread's complete register set. It can also alter the registers, so that the thread continues to run with the modified register set. Is there anything more you need? > Before implementing the syscall, I need to better understand the > kernel-part of Fiasco.OC. Can you help me answer the following questions > and point me to the source code regarding each question: > > * Where (in the source code) are threads preempted and their register > state stored? A thread's userland registers are stored on every entry to the kernel. The class in Fiasco is called Entry_frame. The userland exception handler mentioned above modifies that Entry_frame. > * Where is the register state of a thread loaded to the CPU and the > thread started (e.g. after a preempt)? When the scheduler selects a thread, its userland state (Entry_frame) is restored on exit from kernel mode. > * How can I introspect the stored thread register of a thread in the > kernel debugger JDB? > ** My thoughts: Is it K<kobj_ptr> with kobj_ptr of the thread and the 3 > lines beginning with PC=...? > e.g. > " > PC=010579cc USP=200ffdb0 smlatbeq r9, r0, r2, r5 > [0] 00000003 000010c0 00218003 00000000 tsteq000r5, ip, rrx > [8] 200ffdb0 200ffe40 01086ef0 200ffe98 [c] 200ffef8 010579cc fffffff8 > 20000010 > " Yes, that PC line is the userland program counter. the USP is the userland stack pointer. All userland registers are located at the top of kernel stack for a particular thread. > I also have another, short, off-topic question: > * How can I introspect the capability space of a task inside the kernel > debugger? In short mode, press 's' for a list of all tasks. Select the task in question and the press 'o' to see the capability space for that task. Hope that helps, - Christian

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Extending l4sys by reading/writing register values of a preempted thread
by Denis Huber 13 Mar '17

13 Mar '17

Dear L4 hackers community, I want to implement a new syscall for getting/setting stored register values of a specific thread (identified by its cap). Preliminary note: I'm using the ARM architecture. Before implementing the syscall, I need to better understand the kernel-part of Fiasco.OC. Can you help me answer the following questions and point me to the source code regarding each question: * Where (in the source code) are threads preempted and their register state stored? * Where is the register state of a thread loaded to the CPU and the thread started (e.g. after a preempt)? * Where is the register state stored of each thread? * How can I introspect the stored thread register of a thread in the kernel debugger JDB? ** My thoughts: Is it K<kobj_ptr> with kobj_ptr of the thread and the 3 lines beginning with PC=...? e.g. " PC=010579cc USP=200ffdb0 smlatbeq r9, r0, r2, r5 [0] 00000003 000010c0 00218003 00000000 tsteq000r5, ip, rrx [8] 200ffdb0 200ffe40 01086ef0 200ffe98 [c] 200ffef8 010579cc fffffff8 20000010 " I also have another, short, off-topic question: * How can I introspect the capability space of a task inside the kernel debugger? Kind regards, Denis

1 0

Run L4Re/Fiasco hello example under QEMU (ARM)
by Piotr Piwko 05 Mar '17

05 Mar '17

Hi, I would like to run hello example under qemu-system-arm, so I successfully built the images using gcc-linaro-6.3.1 toolchain with following configuration: L4Re: Target Architecture (ARM architecture) CPU variant (ARMv7A type CPU) Platform Selection (ARM Integrator) Fiasco: Architecture (ARM processor family) Platform (ARM Integrator Platform) CPU (ARM 926 Processor) Unfortunately, after booting boostrap_hello.elf image under qemu-system-arm (the latest 2.8.0 version) there is nothing printed out on the console: $ QEMU_OPTIONS="-machine integratorcp -m 256 -serial mon:stdio -nographic" make qemu E=hello MODULE_SEARCH_PATH=/path/to/fiasco/build/ Do you have any idea what I omitted or what is wrong in my setup? Thank you in advance for your help. -- Piotr Piwko http://www.embedded-engineering.pl/

2 1

read/write to virtual address
by Daniel Krefft 17 Feb '17

17 Feb '17

Hello, while working on a checkpoint/restore mechanism for fiasco.oc, we want to trace read and write (kernel) calls to (virtual) memory. 1) Where are these calls defined? We're just able to find ARM specific calls inside the kernel, which allow writing and reading to/from a virtual address 2) Are these calls (if existent) platform agnostic (user-space)? Is there any kind of interface? Best regards -- Daniel Krefft MSc. Wissenschaftlicher Mitarbeiter Technische Universitaet Muenchen Fakultaet fuer Informatik Lehrstuhl fuer Betriebssysteme Arcisstrasse 21 80333 Muenchen Tel. +49 89 289 18791 daniel.krefft(a)tum.de www.os.in.tum.de/personen/krefft

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